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https://github.com/darlinghq/darling.git
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Lubos Dolezel
307 lines
8.5 KiB
C
307 lines
8.5 KiB
C
/*
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* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
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*
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* This file contains Original Code and/or Modifications of Original Code
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* as defined in and that are subject to the Apple Public Source License
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* Version 2.0 (the 'License'). You may not use this file except in
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* compliance with the License. The rights granted to you under the License
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* may not be used to create, or enable the creation or redistribution of,
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* unlawful or unlicensed copies of an Apple operating system, or to
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* circumvent, violate, or enable the circumvention or violation of, any
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* terms of an Apple operating system software license agreement.
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*
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* Please obtain a copy of the License at
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* http://www.opensource.apple.com/apsl/ and read it before using this file.
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*
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* The Original Code and all software distributed under the License are
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* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
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* Please see the License for the specific language governing rights and
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* limitations under the License.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
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*/
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/* Copyright (c) 1996 NeXT Software, Inc. All rights reserved.
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*
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* File: architecture/ppc/basic_regs.h
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* Author: Doug Mitchell, NeXT Software, Inc.
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*
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* Basic ppc registers.
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*
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* HISTORY
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* 22-May-97 Umesh Vaishampayan (umeshv@apple.com)
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Updated to match MPCFPE32B/AD 1/97 REV. 1
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* 29-Dec-96 Umesh Vaishampayan (umeshv@NeXT.com)
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* Ported from m98k.
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* 05-Nov-92 Doug Mitchell at NeXT
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* Created.
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*/
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#ifndef _ARCH_PPC_BASIC_REGS_H_
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#define _ARCH_PPC_BASIC_REGS_H_
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#include <architecture/ppc/reg_help.h>
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#include <architecture/ppc/macro_help.h>
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#if !defined(__ASSEMBLER__)
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/*
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* Number of General Purpose registers.
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*/
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#define PPC_NGP_REGS 32
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/*
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* Common half-word used in Machine State Register and in
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* various exception frames. Defined as a macro because the compiler
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* will align a struct to a word boundary when used inside another struct.
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*/
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#define MSR_BITS \
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unsigned ee:BIT_WIDTH(15), /* external intr enable */ \
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pr:BIT_WIDTH(14), /* problem state */ \
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fp:BIT_WIDTH(13), /* floating point avail */ \
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me:BIT_WIDTH(12), /* machine check enable */ \
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fe0:BIT_WIDTH(11), /* fp exception mode 0 */ \
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se:BIT_WIDTH(10), /* single step enable */ \
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be:BIT_WIDTH(9), /* branch trace enable */ \
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fe1:BIT_WIDTH(8), /* fp exception mode 0 */ \
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rsvd1:BIT_WIDTH(7), /* reserved */ \
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ip:BIT_WIDTH(6), /* interrupt prefix */ \
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ir:BIT_WIDTH(5), /* instruction relocate */ \
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dr:BIT_WIDTH(4), /* data relocate */ \
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rsvd2:BITS_WIDTH(3,2), /* reserved */ \
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ri:BIT_WIDTH(1), /* recoverable exception */ \
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le:BIT_WIDTH(0) /* Little-endian mode */
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/*
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* Machine state register.
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* Read and written via get_msr() and set_msr() inlines, below.
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*/
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typedef struct {
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unsigned rsvd3:BITS_WIDTH(31,19), // reserved
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pow:BIT_WIDTH(18), // Power management enable
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rsvd0: BIT_WIDTH(17), // reserved
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ile: BIT_WIDTH(16); // exception little endian
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MSR_BITS; // see above
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} msr_t;
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/*
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* Data Storage Interrupt Status Register (DSISR)
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*/
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typedef struct {
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unsigned dse:BIT_WIDTH(31); // direct-store error
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unsigned tnf:BIT_WIDTH(30); // translation not found
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unsigned :BITS_WIDTH(29,28);
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unsigned pe:BIT_WIDTH(27); // protection error
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unsigned dsr:BIT_WIDTH(26); // lwarx/stwcx to direct-store
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unsigned rw:BIT_WIDTH(25); // 1 => store, 0 => load
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unsigned :BITS_WIDTH(24,23);
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unsigned dab:BIT_WIDTH(22); // data address bkpt (601)
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unsigned ssf:BIT_WIDTH(21); // seg table search failed
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unsigned :BITS_WIDTH(20,0);
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} dsisr_t;
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/*
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* Instruction Storage Interrupt Status Register (really SRR1)
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*/
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typedef struct {
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unsigned :BIT_WIDTH(31);
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unsigned tnf:BIT_WIDTH(30); // translation not found
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unsigned :BIT_WIDTH(29);
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unsigned dse:BIT_WIDTH(28); // direct-store fetch error
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unsigned pe:BIT_WIDTH(27); // protection error
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unsigned :BITS_WIDTH(26,22);
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unsigned ssf:BIT_WIDTH(21); // seg table search failed
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unsigned :BITS_WIDTH(20,16);
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MSR_BITS;
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} isisr_t;
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/*
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* Alignment Interrupt Status Register (really DSISR)
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* NOTE: bit numbers in field *names* are in IBM'ese (0 is MSB).
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* FIXME: Yuck!!! Double Yuck!!!
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*/
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typedef struct {
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unsigned :BITS_WIDTH(31,20);
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unsigned ds3031:BITS_WIDTH(19,18);// bits 30:31 if DS form
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unsigned :BIT_WIDTH(17);
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unsigned x2930:BITS_WIDTH(16,15); // bits 29:30 if X form
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unsigned x25:BIT_WIDTH(14); // bit 25 if X form or
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// bit 5 if D or DS form
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unsigned x2124:BITS_WIDTH(13,10); // bits 21:24 if X form or
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// bits 1:4 if D or DS form
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unsigned all615:BITS_WIDTH(9,0); // bits 6:15 of instr
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MSR_BITS;
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} aisr_t;
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/*
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* Program Interrupt Status Register (really SRR1)
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*/
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typedef struct {
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unsigned :BITS_WIDTH(31,21);
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unsigned fpee:BIT_WIDTH(20); // floating pt enable exception
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unsigned ill:BIT_WIDTH(19); // illegal instruction
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unsigned priv:BIT_WIDTH(18); // privileged instruction
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unsigned trap:BIT_WIDTH(17); // trap program interrupt
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unsigned subseq:BIT_WIDTH(16); // 1 => SRR0 points to
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// subsequent instruction
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MSR_BITS;
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} pisr_t;
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/*
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* Condition register. May not be useful in C, let's see...
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*/
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typedef struct {
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unsigned lt:BIT_WIDTH(31), // negative
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gt:BIT_WIDTH(30), // positive
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eq:BIT_WIDTH(29), // equal to zero
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so:BIT_WIDTH(28), // summary overflow
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fx:BIT_WIDTH(27), // floating point exception
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fex:BIT_WIDTH(26), // fp enabled exception
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vx:BIT_WIDTH(25), // fp invalid operation
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// exception
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ox:BIT_WIDTH(24), // fp overflow exception
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rsvd:BITS_WIDTH(23,0); // reserved
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} cr_t;
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/*
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* Abstract values representing fe0:fe1.
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* See get_fp_exc_mode(), below.
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*/
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typedef enum {
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FEM_IGNORE_EXCEP, // ignore exceptions
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FEM_IMPR_NONREC, // imprecise nonrecoverable
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FEM_IMPR_RECOV, // imprecise recoverable
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FEM_PRECISE
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} fp_exc_mode_t;
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/*
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* Special purpose registers.
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*/
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/*
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* Processor version register (special purpose register pvr).
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*/
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typedef struct {
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unsigned version:BITS_WIDTH(31,16),
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revision:BITS_WIDTH(15,0);
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} pvr_t;
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/*
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* Fixed point exception register (special purpose register xer)
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*/
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typedef struct {
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unsigned so:BIT_WIDTH(31), // summary overflow
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ov:BIT_WIDTH(30), // overflow
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ca:BIT_WIDTH(29), // carry
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rsvd1:BITS_WIDTH(28,7), // reserved
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byte_count:BITS_WIDTH(6,0);
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} xer_t;
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/*
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* Inlines and macros to manipulate the above registers.
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*/
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/*
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* Get/set machine state register.
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*/
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static __inline__ msr_t
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get_msr()
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{
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msr_t __msr_tmp;
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__asm__ volatile ("mfmsr %0 /* mfmsr */" : "=r" (__msr_tmp));
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return __msr_tmp;
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}
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static __inline__ void
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set_msr(msr_t msr)
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{
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__asm__ volatile ("mtmsr %0 /* mtmsr */ " : : "r" (msr));
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}
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/*
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* Determine current fp_exc_mode_t given prog_mode.
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*/
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static __inline__ fp_exc_mode_t
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get_fp_exc_mode(pmr_t pmr)
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{
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if(pmr.fe0)
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return pmr.fe1 ? FEM_PRECISE : FEM_IMPR_RECOV;
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else
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return pmr.fe1 ? FEM_IMPR_NONREC : FEM_IGNORE_EXCEP;
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}
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/*
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* Software definitions for special purpose registers.
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* The same register is used as per_cpu data pointer and
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* vector base register. This requires that the vector
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* table be the first item in the per_cpu table.
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*/
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#define SR_EXCEPTION_TMP_LR sprg0
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#define SR_EXCEPTION_TMP_CR sprg1
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#define SR_EXCEPTION_TMP_AT sprg2
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#define SR_PER_CPU_DATA sprg3
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#define SR_VBR sprg3
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/*
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* Get/set special purpose registers.
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*
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* GET_SPR - get SPR by name.
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*
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* Example usage:
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*
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* {
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* xer_t some_xer;
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*
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* some_xer = GET_SPR(xer_t, xer);
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* ...
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* }
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*
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* This is a strange one. We're creating a list of C expressions within
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* a set of curlies; the last expression ("__spr_tmp;") is the return value
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* of the statement created by the curlies.
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*
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*/
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#define GET_SPR(type, spr) \
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({ \
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unsigned __spr_tmp; \
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__asm__ volatile ("mfspr %0, " STRINGIFY(spr) : "=r" (__spr_tmp)); \
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*(type *)&__spr_tmp; \
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})
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/*
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* Example usage of SET_SPR:
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*
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* {
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* xer_t some_xer;
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*
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* ...set up some_xer...
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* SET_SPR(xer, some_xer);
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* }
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*/
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#define SET_SPR(spr, val) \
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MACRO_BEGIN \
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__typeof__ (val) __spr_tmp = (val); \
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__asm__ volatile ("mtspr "STRINGIFY(spr) ", %0" : : "r" (__spr_tmp)); \
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MACRO_END
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/*
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* Fully synchronize instruction stream.
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*/
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static __inline__ void
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ppc_sync()
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{
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__asm__ volatile ("sync /* sync */" : : );
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}
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#endif /* ! __ASSEMBLER__ */
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#endif /* _ARCH_PPC_BASIC_REGS_H_ */
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