From 270e6867dbd0c6767acadae4ceecfd1728afe88a Mon Sep 17 00:00:00 2001 From: philpem Date: Thu, 17 Oct 2024 00:10:26 +0100 Subject: [PATCH 1/4] Update 6805.slaspec Fix for https://github.com/NationalSecurityAgency/ghidra/issues/7064 (incorrect handling of X-indexed JMP and JSR) --- Ghidra/Processors/MC6800/data/languages/6805.slaspec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/MC6800/data/languages/6805.slaspec b/Ghidra/Processors/MC6800/data/languages/6805.slaspec index 7edef3f495..89c0c4da87 100644 --- a/Ghidra/Processors/MC6800/data/languages/6805.slaspec +++ b/Ghidra/Processors/MC6800/data/languages/6805.slaspec @@ -373,7 +373,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; } :JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI { - goto [ADDRI]; + goto ADDRI; } @@ -387,7 +387,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; } { *:2 (SP-1) = inst_next; SP=SP-2; - call [ADDRI]; + call ADDRI; } :LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1 From 67bfea173fc03dae728c07cc468e51e360b14367 Mon Sep 17 00:00:00 2001 From: philpem Date: Thu, 17 Oct 2024 01:24:10 +0100 Subject: [PATCH 2/4] Update HCS_HC.sinc Fixes https://github.com/NationalSecurityAgency/ghidra/issues/7064 for 68HC05 --- Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc index 3e6d10db34..1795c9ca8e 100644 --- a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc +++ b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc @@ -1258,7 +1258,7 @@ macro Push2(operand) { @if defined(HCS08) || defined(HC08) || defined(HC05) :JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI { - goto [ADDRI]; + goto ADDRI; } @endif @@ -1278,7 +1278,7 @@ macro Push2(operand) { tmp:2 = inst_next; Push2( tmp ); - call [ADDRI]; + call ADDRI; } @endif From e04e47a7454df0c0e489e81311c8592ac418f279 Mon Sep 17 00:00:00 2001 From: philpem Date: Tue, 29 Oct 2024 19:25:20 +0000 Subject: [PATCH 3/4] Update HCS_HC.sinc Incorporate fixes from PR --- .../HCS08/data/languages/HCS_HC.sinc | 23 +++++++++---------- 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc index 1795c9ca8e..9072d64f23 100644 --- a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc +++ b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc @@ -114,15 +114,15 @@ oprx8_16_SP: imm8,SP is imm8 & SP { address:2 = SP + imm8; export *:2 addres # X or HIX addressing @if defined(HC05) -oprx8_8_X: imm8,X is imm8 & X { address:2 = zext(X) + imm8; export *:1 address; } -oprx16_8_X: imm16,X is imm16 & X { address:2 = zext(X) + imm16; export *:1 address; } -comma_X: ","X is X { address:2 = zext(X); export *:1 address; } +oprx8_8_X: imm8,X is imm8 & X { address:2 = zext(X) + imm8; export address; } +oprx16_8_X: imm16,X is imm16 & X { address:2 = zext(X) + imm16; export address; } +comma_X: ","X is X { address:2 = zext(X); export address; } @endif @if defined(HCS08) || defined(HC08) -oprx8_8_X: imm8,X is imm8 & X { address:2 = HIX + imm8; export *:1 address; } -oprx16_8_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export *:1 address; } -comma_X: ","X is X { address:2 = HIX; export *:1 address; } +oprx8_8_X: imm8,X is imm8 & X { address:2 = HIX + imm8; export address; } +oprx16_8_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export address; } +comma_X: ","X is X { address:2 = HIX; export address; } @endif @if defined(HCS08) @@ -136,9 +136,9 @@ oprx16_16_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export *:2 a OP1: iopr8i is op4_6=2; iopr8i { export iopr8i; } OP1: opr8a_8 is op4_6=3; opr8a_8 { export opr8a_8; } OP1: opr16a_8 is op4_6=4; opr16a_8 { export opr16a_8; } -OP1: oprx16_8_X is op4_6=5; oprx16_8_X { export oprx16_8_X; } -OP1: oprx8_8_X is op4_6=6; oprx8_8_X { export oprx8_8_X; } -OP1: comma_X is op4_6=7 & comma_X { export comma_X; } +OP1: oprx16_8_X is op4_6=5; oprx16_8_X { export *:1 oprx16_8_X; } +OP1: oprx8_8_X is op4_6=6; oprx8_8_X { export *:1 oprx8_8_X; } +OP1: comma_X is op4_6=7 & comma_X { export *:1 comma_X; } @if defined(HCS08) || defined(HC08) op2_opr8a: imm8 is imm8 { export *:1 imm8; } @@ -1258,7 +1258,7 @@ macro Push2(operand) { @if defined(HCS08) || defined(HC08) || defined(HC05) :JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI { - goto ADDRI; + goto [ADDRI]; } @endif @@ -1278,7 +1278,7 @@ macro Push2(operand) { tmp:2 = inst_next; Push2( tmp ); - call ADDRI; + call [ADDRI]; } @endif @@ -2074,4 +2074,3 @@ macro Push2(operand) { wait(); } @endif - From c86d9069c577f7a88f7ab59da1113fdd14ad7ff0 Mon Sep 17 00:00:00 2001 From: philpem Date: Tue, 29 Oct 2024 19:31:21 +0000 Subject: [PATCH 4/4] Update 6805.slaspec --- .../Processors/MC6800/data/languages/6805.slaspec | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/Ghidra/Processors/MC6800/data/languages/6805.slaspec b/Ghidra/Processors/MC6800/data/languages/6805.slaspec index 89c0c4da87..f314c0a311 100644 --- a/Ghidra/Processors/MC6800/data/languages/6805.slaspec +++ b/Ghidra/Processors/MC6800/data/languages/6805.slaspec @@ -42,13 +42,13 @@ OP1: imm8 is op4_6=3; imm8 { export *:1 imm8; } OP1: imm16 is op4_6=4; imm16 { export *:1 imm16; } OP1: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; } OP1: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; } -OP1: X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; } +OP1: ","X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; } ADDR: imm8 is op4_6=3; imm8 { export *:1 imm8; } ADDR: imm16 is op4_6=4; imm16 { export *:1 imm16; } -ADDRI: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export tmp; } -ADDRI: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export tmp; } -ADDRI: X is op4_6=7 & X { tmp:2 = zext(X); export tmp; } +ADDRI: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; } +ADDRI: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; } +ADDRI: ","X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; } DIRECT: imm8 is imm8 { export *:1 imm8; } @@ -373,7 +373,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; } :JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI { - goto ADDRI; + goto [ADDRI]; } @@ -387,7 +387,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; } { *:2 (SP-1) = inst_next; SP=SP-2; - call ADDRI; + call [ADDRI]; } :LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1 @@ -666,4 +666,3 @@ DIRECT: imm8 is imm8 { export *:1 imm8; } { I = 0; } -