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emteere_GT-2902 minor syntax changes to sleigh file. No effect to

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languages.
This commit is contained in:
emteere
2019-06-10 17:44:49 -04:00
parent d0ee2aa26b
commit 6ea9e0a93f
9 changed files with 270 additions and 269 deletions
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Ghidra/Processors/6805/data/languages/6805.slaspec
+46 -46
View File
@@ -55,16 +55,16 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
{
op1 = OP1;
local op1 = OP1;
# compute half carry
halfop1 = op1 & 0xF;
halfA = A & 0xF;
halfresult = halfop1 + halfA + C;
local halfop1 = op1 & 0xF;
local halfA = A & 0xF;
local halfresult = halfop1 + halfA + C;
H = (halfresult >> 4) & 1;
result = A + op1;
tmpC = carry(A, op1);
local result = A + op1;
local tmpC = carry(A, op1);
A = result + C;
C = carry(result, C);
@@ -74,12 +74,12 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
{
op1 = OP1;
local op1 = OP1;
# compute half carry
halfop1 = op1 & 0xF;
halfA = A & 0xF;
halfresult = halfop1 + halfA;
local halfop1 = op1 & 0xF;
local halfA = A & 0xF;
local halfresult = halfop1 + halfA;
H = (halfresult >> 4) & 1;
C = carry(A, op1);
@@ -111,7 +111,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
{
tmp = OP1;
local tmp = OP1;
C = tmp >> 7;
tmp = tmp << 1;
OP1 = tmp;
@@ -134,7 +134,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
{
tmp = OP1;
local tmp = OP1;
C = tmp & 1;
tmp = tmp s>> 1;
OP1 = tmp;
@@ -148,7 +148,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:BCLR n,DIRECT is op4_7=1 & bit_0=1 & n; DIRECT {
mask = ~(1 << n);
local mask = ~(1 << n);
DIRECT = DIRECT & mask;
}
:BCS REL is op=0x25;REL
@@ -169,7 +169,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:BHI REL is op=0x22;REL
{
tmp = C + Z;
local tmp = C + Z;
if (tmp == 0) goto REL;
}
@@ -187,7 +187,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
{
result = A & OP1;
local result = A & OP1;
Z = (result == 0);
N = (result s< 0);
}
@@ -195,7 +195,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:BLS REL is op=0x23;REL
{
tmp = C + Z;
local tmp = C + Z;
if (tmp) goto REL;
}
@@ -230,18 +230,18 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:BRCLR n,DIRECT,REL is op4_7=0 & bit_0=1 & n; DIRECT; REL
{
mask = (1 << n);
result = DIRECT & mask;
local mask = (1 << n);
local result = DIRECT & mask;
if (result == 0) goto REL;
}
:BRSET n,DIRECT,REL is op4_7=0 & bit_0=0 & n; DIRECT; REL
{
mask = (1 << n);
result = DIRECT & mask;
local mask = (1 << n);
local result = DIRECT & mask;
if (result != 0) goto REL;
}
:BSET n,DIRECT is op4_7=1 & bit_0=0 & n; DIRECT {
mask = ~(1 << n);
local mask = ~(1 << n);
DIRECT = DIRECT & mask;
}
:BSR REL is op=0xAD; REL
@@ -281,8 +281,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
{
op1 = OP1;
tmp = A - op1;
local op1 = OP1;
local tmp = A - op1;
Z = tmp == 0;
N = tmp s< 0;
C = (A < op1);
@@ -304,7 +304,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
{
tmp = ~OP1;
local tmp = ~OP1;
OP1 = tmp;
Z = (tmp == 0);
N = (tmp s< 0);
@@ -312,8 +312,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
{
op1 = OP1;
tmp = X - op1;
local op1 = OP1;
local tmp = X - op1;
Z = tmp == 0;
N = tmp s< 0;
C = (A < op1);
@@ -332,14 +332,14 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
{
tmp = OP1 - 1;
local tmp = OP1 - 1;
OP1 = tmp;
Z = (tmp == 0);
N = (tmp s< 0);
}
:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
{
op1 = OP1;
local op1 = OP1;
A = A ^ op1;
Z = A == 0;
N = A s< 0;
@@ -358,7 +358,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
{
tmp = OP1 + 1;
local tmp = OP1 + 1;
OP1 = tmp;
Z = (tmp == 0);
N = (tmp s< 0);
@@ -421,7 +421,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
{
tmp = OP1;
local tmp = OP1;
C = tmp & 1;
tmp = tmp >> 1;
OP1 = tmp;
@@ -433,7 +433,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
{
op1:2 = zext(A);
op2:2 = zext(X);
result = op1 * op2;
local result = op1 * op2;
A = result:1;
result = result >> 8;
X = result:1;
@@ -455,7 +455,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
{
op1 = OP1;
local op1 = OP1;
C = op1 != 0;
OP1 = -op1;
Z = (op1 == 0);
@@ -475,7 +475,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:ROLA is op=0x49
{
tmp = C ;
local tmp = C ;
C = A >> 7;
A = A << 1;
A = A | tmp;
@@ -484,7 +484,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ROLX is op=0x59
{
tmp = C;
local tmp = C;
C = X >> 7;
X = X << 1;
X = X | tmp;
@@ -493,10 +493,10 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
{
tmpC = C;
op1 = OP1;
local tmpC = C;
local op1 = OP1;
C = op1 >> 7;
result = op1 << 1;
local result = op1 << 1;
result = result | tmpC;
OP1 = result;
Z = (result == 0);
@@ -504,7 +504,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:RORA is op=0x46
{
tmpC = C << 7;
local tmpC = C << 7;
C = A & 1;
A = A s>> 1;
A = A | tmpC;
@@ -513,7 +513,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:RORX is op=0x56
{
tmpC = C << 7;
local tmpC = C << 7;
C = X & 1;
X = X s>> 1;
X = X | tmpC;
@@ -522,8 +522,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
{
tmpC = C << 7;
tmp = OP1;
local tmpC = C << 7;
local tmp = OP1;
C = tmp & 1;
tmp = tmp s>> 1;
tmp = tmp | tmpC;
@@ -540,7 +540,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:RTI is op = 0x80
{
SP = SP+1;
ccr = *:1 SP;
local ccr = *:1 SP;
H = ccr[4,1];
I = ccr[3,1];
N = ccr[2,1];
@@ -570,8 +570,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
{
op1 = OP1;
tmp = A - op1 - C;
local op1 = OP1;
local tmp = A - op1 - C;
Z = tmp == 0;
N = tmp s< 0;
C = ((A <= op1) * C) | (A < op1);
@@ -609,7 +609,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
{
op1 = OP1;
local op1 = OP1;
C = (A < op1);
A = A - op1;
Z = A == 0;
@@ -648,7 +648,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
}
:TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
{
op1 = OP1;
local op1 = OP1;
Z = (op1 == 0);
N = (op1 s< 0);
}
Ghidra/Processors/8051/data/languages/mx51.sinc
+1 -1
View File
@@ -190,7 +190,7 @@ EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0
:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg {
*:1 EPTR = ACC;
}
:movc Areg,"@"APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
ACC = *:1 APlusEptr;
}
:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR {
Ghidra/Processors/8085/data/languages/8085.slaspec
+1 -1
View File
@@ -90,7 +90,7 @@ macro setAddFlags(op1,op2) {
}
macro setSubtractCarryFlags(op1,op2) {
notC = ~CY_flag;
local notC = ~CY_flag;
CY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC))));
}
Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
+20 -20
View File
@@ -432,10 +432,10 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16
simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16);
* [register]:1 tmp3 = (* [register]:1 tmp1) + (* [register]:1 tmp2);
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
Zd = zext(tmpd); # assigning to Rd_VPR128.16B
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128.16B = NEON_add(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
@endif
}
@@ -526,10 +526,10 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S
simd_address_at(tmp3, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2);
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128.4S = NEON_add(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
@endif
}
@@ -682,10 +682,10 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S
simd_address_at(tmp3, Rd_VPR64.2S, 1, 4, 8);
* [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2);
zext_zd(Zd); # zero upper 24 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmpd:8 = SIMD_INT_ADD(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
Zd = zext(tmpd); # assigning to Rd_VPR64.2S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR64.2S = NEON_add(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
@endif
}
@@ -1658,7 +1658,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x
local tmp10:4 = tmp7 + tmp9;
Rd_FPR32 = tmp5 + tmp10;
zext_zs(Zd); # zero upper 28 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Rn_VPR128.4S, 0:1);
local tmp2:4 = SIMD_PIECE(Rn_VPR128.4S, 1:1);
local tmp3:4 = tmp1 + tmp2;
@@ -1667,7 +1667,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x
local tmp6:4 = tmp4 + tmp5;
local tmpd:4 = tmp3 + tmp6;
Zd = zext(tmpd); # assigning to Rd_FPR32
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_FPR32 = NEON_addv(Rn_VPR128.4S, 4:1);
@endif
}
@@ -4291,11 +4291,11 @@ is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x
simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16);
* [register]:1 tmp3 = tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmp1:1 = SIMD_PIECE(Rn_GPR32, 0:1);
local tmpd:16 = SIMD_COPY(Rd_VPR128.16B, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.16B
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128.16B = NEON_dup(Rd_VPR128.16B, Rn_GPR32, 1:1);
@endif
}
@@ -19165,10 +19165,10 @@ is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2
simd_address_at(tmp1, Rd_VPR128, imm_neon_uimm2:4, 4, 16);
* [register]:4 tmp1 = Rn_GPR32;
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_COPY(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1);
Zd = zext(tmpd); # assigning to Rd_VPR128
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128 = NEON_mov(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1, 2:1);
@endif
}
@@ -19232,11 +19232,11 @@ is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2
local tmp2:4 = * [register]:4 tmp1;
Rd_GPR32 = tmp2;
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1);
local tmpd:4 = tmp1;
Rd_GPR64 = zext(tmpd); # assigning to Rd_GPR32
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1);
Rd_GPR32 = NEON_mov(tmp1, 4:1);
@endif
@@ -19366,11 +19366,11 @@ is b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01
simd_address_at(tmp2, Rd_VPR128.2D, 1, 8, 16);
* [register]:8 tmp2 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmp1:8 = Imm_neon_uimm8Shift;
local tmpd:16 = SIMD_COPY(Rd_VPR128.2D, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.2D
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128.2D = NEON_movi(Imm_neon_uimm8Shift, 8:1);
@endif
}
@@ -19468,10 +19468,10 @@ is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b0
simd_address_at(tmp1, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp1 = Imm_neon_uimm8Shift:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_COPY(Rd_VPR128.4S, Imm_neon_uimm8Shift:4);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
Rd_VPR128.4S = NEON_movi(Imm_neon_uimm8Shift, 4:1);
@endif
}
@@ -19674,11 +19674,11 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re
simd_address_at(tmp4, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp4 = (* [register]:4 tmp3) * tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
local tmpd:16 = SIMD_INT_MULT(Rn_VPR128.4S, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force)
@elif defined(SEMANTIC_pseudo)
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_mul(Rn_VPR128.4S, tmp1, 4:1);
@endif
Ghidra/Processors/Dalvik/data/languages/Dalvik.slaspec
+5 -5
View File
@@ -500,7 +500,7 @@ define pcodeop switchAssist;
# A: destination register (8 bits)
# B: arbitrary 32-bit constant
:const registerA8,constant32 is inst0=0x14 ; registerA8 ; constant32
:"const" registerA8,constant32 is inst0=0x14 ; registerA8 ; constant32
{
registerA8 = constant32;
}
@@ -808,11 +808,11 @@ define pcodeop switchAssist;
distance:4 = B_BITS_0_31_S * 2;
ident:4 = *[ram] ( inst_start + distance );
size2:2 = *[ram] ( inst_start + distance + 2 );
size:4 = zext( size2 );
sze:4 = zext( size2 );
first_key:4 = *[ram] ( inst_start + distance + 2 + 2 );
if ( registerA8 < first_key ) goto inst_next;
if ( registerA8 >= ( first_key + size ) ) goto inst_next;
if ( registerA8 >= ( first_key + sze ) ) goto inst_next;
targets:4 = ( inst_start + distance + 2 + 2 + 4 );
delta:4 = ( registerA8 ) - ( first_key ); # which index into target
@@ -836,11 +836,11 @@ define pcodeop switchAssist;
distance:4 = B_BITS_0_31_S * 2;
temp:4 = inst_start;
size2:2 = *[ram] ( temp + 2 + distance);
size:4 = zext( size2 );
sze:4 = zext( size2 );
defaultPos:4 = inst_next;
address:4 = switchAssist( registerA8, size, defaultPos, temp, distance );
address:4 = switchAssist( registerA8, sze, defaultPos, temp, distance );
goto [ address ];
}
Ghidra/Processors/PA-RISC/data/languages/pa-risc.sinc
+115 -114
View File
@@ -158,7 +158,7 @@ define context contextreg
temp32 = (64,95) noflow
;
@define COMMON "& phase=1 "
@define COMMON "phase=1 "
# Instruction fields
@@ -214,6 +214,7 @@ define token instr(32)
u = (13,13)
fpr1x = (12,12)
f = (12,12)
fv = (12,12)
zero = (12,12)
one = (12,12)
subop1012 = (10,12)
@@ -437,7 +438,7 @@ attach names [ fusedfmt ] [
# previous instruction was not a branch, but may have conditionally nullified this instruction
:^instruction is phase=0 & branchEnable=0 & nullifyEnable=1 & instruction [ phase=1; ] {
wasNullified = nullifyCond;
local wasNullified = nullifyCond;
nullifyCond = 0;
nullifyNextCond=0;
if (wasNullified) goto <skip>;
@@ -462,7 +463,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -486,7 +487,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -514,9 +515,9 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
build instruction;
if (previousBranchCond && previousBranchExecuted) goto immediateDest;
@@ -531,7 +532,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
nullifyCond = 0;
nullifyNextCond = 0;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
build instruction;
if (previousBranchCond) goto immediateDest;
@@ -540,8 +541,8 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC)
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
previousBranchCond = branchCond;
local previousBranchExecuted = branchExecuted;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -554,7 +555,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC)
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {
nullifyNextCond=0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -570,7 +571,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=1 & branchType=4 & instruction [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
build instruction;
if ( ! previousBranchExecuted ) goto <skip>;
@@ -604,7 +605,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
build instruction;
if ( ! previousBranchExecuted ) goto <skip>;
@@ -628,8 +629,8 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
previousBranchCond = branchCond;
local previousBranchExecuted = branchExecuted;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -646,7 +647,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
nullifyCond = 0;
nullifyNextCond=0;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
build instruction;
if ( ! previousBranchCond ) goto <skip>;
@@ -659,8 +660,8 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullifyCond = 0;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
previousBranchCond = branchCond;
local previousBranchExecuted = branchExecuted;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
build instruction;
@@ -675,7 +676,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
nullifyCond = 0;
nullifyNextCond=0;
branchExecuted = 0;
previousBranchCond= branchCond;
local previousBranchCond= branchCond;
branchCond = 0;
build instruction;
if ( ! previousBranchCond) goto <skip>;
@@ -690,10 +691,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 0, unconditional immediate branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
if (nullify) goto <skip>;
build instruction;
@@ -704,7 +705,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 0, unconditional immediate branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
branchExecuted = 0;
@@ -716,10 +717,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 1, unconditional immediate call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
if (nullify) goto <skip>;
build instruction;
@@ -732,7 +733,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 1, unconditional immediate call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
branchExecuted = 0;
@@ -744,12 +745,12 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 2, conditional immediate branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
if (nullify) goto <skip>;
build instruction;
@@ -760,11 +761,11 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 2, conditional immediate branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond=0;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0; # Need to reset branchCond
if (nullify) goto <skip>;
build instruction;
@@ -775,10 +776,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 3, conditional immediate call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
previousBranchCond = branchCond;
local previousBranchExecuted = branchExecuted;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
if (nullify) goto <wasnullified>;
@@ -792,9 +793,9 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 3, conditional immediate call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyNextCond=0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
branchExecuted = 0;
if (nullify) goto <wasnullified>;
@@ -808,10 +809,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 4, unconditional indirect branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -824,7 +825,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 4, unconditional indirect branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=0 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
branchExecuted = 0;
@@ -836,10 +837,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 5, unconditional indirect call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -852,7 +853,7 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 5, unconditional indirect call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=0 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond = 0;
branchExecuted = 0;
@@ -864,12 +865,12 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 6, conditional indirect branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -882,11 +883,11 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 6, conditional indirect branch
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=0 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyCond = 0;
nullifyNextCond=0;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -899,11 +900,11 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 7, conditional indirect call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyNextCond=0;
previousBranchExecuted = branchExecuted;
local previousBranchExecuted = branchExecuted;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -916,10 +917,10 @@ immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; }
# branchType = 7, conditional indirect call
:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=0 & instruction [ phase=1; ] {
nullify = nullifyCond;
local nullify = nullifyCond;
nullifyNextCond=0;
branchExecuted = 0;
previousBranchCond = branchCond;
local previousBranchCond = branchCond;
branchCond = 0;
if (nullify) goto <wasnullified>;
build instruction;
@@ -1271,10 +1272,10 @@ SRRB3bit: (SR3bit,RB) is SR3bit & RB { }
# this first one gets the value in the appropriate space register and returns it.
# it is used by LDSID.
SRVAL: SR is SR & RB & s=0 {
selbits = (RB >> 30);
local selbits = (RB >> 30);
srreg:4 = &sr4 + 4 * selbits;
space:4 = *[register] srreg;
export space;
spc:4 = *[register] srreg;
export spc;
}
SRVAL: sr1 is sr1 & s=1 { export sr1; }
@@ -1284,10 +1285,10 @@ SRVAL: sr3 is sr3 & s=3 { export sr3; }
# TODO This is broken until we decide on how to handle space registers and a 64 bit extended address space
SPCBASE: is SRVAL & RB {
# space:$(ADDRSIZE) = zext(SRVAL);
offset:$(ADDRSIZE) = zext(RB); # need to decide whether to remove the lower bits to hide privilege-- TODO & 0xFFFFFFFFFFFFFFFC;
off:$(ADDRSIZE) = zext(RB); # need to decide whether to remove the lower bits to hide privilege-- TODO & 0xFFFFFFFFFFFFFFFC;
# address:$(ADDRSIZE) = (space << 32) | offset;
# export address;
export offset;
export off;
}
###############################################
@@ -1384,25 +1385,25 @@ shiftCLen: shift is im5 [ shift=32-im5; ] { amount:4 = shift; export amount; }
#lse14: offset is sim14 & bit0 [ offset = (-1 * bit0) * ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; }
#lse14: offset is sim14 & bit0 [ offset = (-1 * 0x2000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = sext(offset:4); export temp; }
lse14: offset is im14less0 & bit0 [ offset = ((-1 * bit0) << 13) | im14less0; ] { temp:4 = sext(offset:4); export temp; }
lse14: offset is im14less0 & bit0 [ local off = ((-1 * bit0) << 13) | im14less0; ] { temp:4 = sext(off:4); export temp; }
####lse14: offset is sim14 & bit0 [ offset = (0xFFFFFFFFFFFFE000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; }
#lse5: offset is sim5 & bit0 [ offset = (-1 * 0x10 * bit0) | ( (sim5 >> 1) & 0xF ); ] { temp:1 = sext(offset:1); export temp; }
lse5: offset is im5less0 & bit0 [ offset = ((-1 * bit0) << 4) | im5less0; ] { temp:1 = sext(offset:1); export temp; }
lse5: offset is im5less0 & bit0 [ local off = ((-1 * bit0) << 4) | im5less0; ] { temp:1 = sext(off:1); export temp; }
#highlse5: offset is highIm5 & bit16 [ offset = (-1 * 0x10 * bit16) | ( (highIm5 >> 1) & 0xF ); ] { temp:1 = offset; export temp; }
highlse5: offset is highIm5less16 & bit16 [ offset = ((-1 * bit16) << 4) | highIm5less16; ] { temp:1 = offset; export temp; }
highlse5: offset is highIm5less16 & bit16 [ local off = ((-1 * bit16) << 4) | highIm5less16; ] { temp:1 = off; export temp; }
#lse21: offset is sim21 [ offset = ( ((sim21 & 0x1) * 0xFFFFFFFFFFF00000) | ((sim21 & 0xFFE) << 8) | ((sim21 & 0xC000) >> 7) | ((sim21 & 0x1F0000) >> 14) | ((sim21 & 0x3000) >> 12) ) << 11 ; ] { temp:$(REGSIZE) = offset; export temp; }
lse21: offset is im21less0 & bit0 & im21_1_12 & im21_12_14 & im21_14_16 & im21_16_21 [
offset = (
local off = (
((-1 * bit0) << 20) |
(im21_1_12 << 9) |
(im21_14_16 << 7) |
(im21_16_21 << 2) |
im21_12_14
) << 11;
] { temp:$(REGSIZE) = offset; export temp; }
] { temp:$(REGSIZE) = off; export temp; }
# Note for the im11 11-bit immediate, the sign is in bit 0, and the rest of the value is in bit 1 to 10.
# Negative numbers are stored 2s complement, with bit0 set to 1.
@@ -1487,17 +1488,17 @@ RegUnitCond: is c=4 { export 0:1; } # some digit carry -- TODO FIGURE OUT BCD
RegUnitCond: is c=6 { export 0:1; } # some byte carry -- TODO BCD
RegUnitCond: is c=7 { export 0:1; } # some halfword carry -- TODO BCD
UnitCond: is RegUnitCond & f=0 { export RegUnitCond; }
UnitCond: is RegUnitCond & f=1 { tmp:1 = ! RegUnitCond; export tmp; }
UnitCond: "" is RegUnitCond & fv=0 { export RegUnitCond; }
UnitCond: "" is RegUnitCond & fv=1 { tmp:1 = ! RegUnitCond; export tmp; }
UnitCondNullify: is c=0 & f=0 { }
UnitCondNullify: is c=0 & fv=0 { }
UnitCondNullify: is UnitCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = UnitCond;
}
UnitCondSym: RegUnitCondSym is RegUnitCondSym & f=0 { }
UnitCondSym: InvUnitCondSym is InvUnitCondSym & f=1 { }
UnitCondSym: RegUnitCondSym is RegUnitCondSym & fv=0 { }
UnitCondSym: InvUnitCondSym is InvUnitCondSym & fv=1 { }
#
##### The Add Conditions from table 5-4 on page 5-5
@@ -1511,17 +1512,17 @@ RegAddCond: is c = 5 & R1 & R2 { tmp:1 = (R1 + R2) == 0 ; export tmp; } # sum
RegAddCond: is c = 6 & R1 & R2 { tmp:1 = scarry(R1,R2); export tmp; } # signed sum overflows
RegAddCond: is c = 7 & R1 & R2 { tmp:1 = ((R1+R2) & 0x1) == 0x1 ; export tmp; } # sum is odd
AddCond: is RegAddCond & f=0 { export RegAddCond; }
AddCond: is RegAddCond & f=1 { tmp:1 = ! RegAddCond; export tmp; }
AddCond: is RegAddCond & fv=0 { export RegAddCond; }
AddCond: is RegAddCond & fv=1 { tmp:1 = ! RegAddCond; export tmp; }
AddCondNullify: is c=0 & f=0 { }
AddCondNullify: is c=0 & fv=0 { }
AddCondNullify: is AddCond [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = AddCond;
}
AddCondSym: RegAddCondSym is RegAddCondSym & f=0 { }
AddCondSym: InvAddCondSym is InvAddCondSym & f=1 { }
AddCondSym: RegAddCondSym is RegAddCondSym & fv=0 { }
AddCondSym: InvAddCondSym is InvAddCondSym & fv=1 { }
RegAddCondI: is c = 0 { export 0:1; } # never
RegAddCondI: is c = 1 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val == -R2) ; export tmp; } # equal to negated
@@ -1571,10 +1572,10 @@ RegAddCondI11: is temp32 & c = 7 & lse11 & R2 {
val:8 = sext(temp32:2); tmp_R2:8 = sext(R2);
tmp:1 = ((val+tmp_R2) & 0x1) == 0x1 ; export tmp; } # sum is odd
AddCondI11: is RegAddCondI11 & f=0 { export RegAddCondI11; }
AddCondI11: is RegAddCondI11 & f=1 { temp:1 = ! RegAddCondI11; export temp; }
AddCondI11: is RegAddCondI11 & fv=0 { export RegAddCondI11; }
AddCondI11: is RegAddCondI11 & fv=1 { temp:1 = ! RegAddCondI11; export temp; }
AddCondI11Nullify: is c=0 & f=0 { }
AddCondI11Nullify: is c=0 & fv=0 { }
AddCondI11Nullify: is AddCondI11 [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = AddCondI11;
@@ -1592,17 +1593,17 @@ RegCSCond: is c=5 & R1 & R2 { tmp:1 = (R1 <= R2) ; export tmp; } # unsigned le
RegCSCond: is c=6 & R1 & R2 { tmp:1 = sborrow(R1,R2) ; export tmp; } # signed minus overflows (borrows)
RegCSCond: is c=7 & R1 & R2 { tmp:1 = ((R1 - R2) & 0x1) == 1 ; export tmp; } # odd
CSCond: is f=0 & RegCSCond { export RegCSCond; }
CSCond: is f=1 & RegCSCond { tmp:1 = ! RegCSCond; export tmp; }
CSCond: is fv=0 & RegCSCond { export RegCSCond; }
CSCond: is fv=1 & RegCSCond { tmp:1 = ! RegCSCond; export tmp; }
CSCondNullify: is c=0 & f=0 { }
CSCondNullify: is c=0 & fv=0 { }
CSCondNullify: is CSCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = CSCond;
}
CSCondSym: RegCSCondSym is RegCSCondSym & f=0 { }
CSCondSym: InvCSCondSym is InvCSCondSym & f=1 { }
CSCondSym: RegCSCondSym is RegCSCondSym & fv=0 { }
CSCondSym: InvCSCondSym is InvCSCondSym & fv=1 { }
# The Compare or Subtract conditions compared with 5 bit immediates
# This is used in the COMIB[TF] instructions. The inverted versions are never used.
@@ -1612,7 +1613,7 @@ RegCSCondI: is c=2 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 =
RegCSCondI: is c=3 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal
RegCSCondI: is c=4 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val < R2) ; export tmp; } # unsigned less than
RegCSCondI: is c=5 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal
RegCSCondI: is c=6 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow
RegCSCondI: is c=6 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow
RegCSCondI: is c=7 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd
# The Compare or Subtract conditions compared with 11 bit immediates. These are used with the SUBI[O] and COMICLR instructions. Both regular and inverted forms are used.
@@ -1622,13 +1623,13 @@ RegCSCondI11: is c=2 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (va
RegCSCondI11: is c=3 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal
RegCSCondI11: is c=4 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val < R2) ; export tmp; } # unsigned less than
RegCSCondI11: is c=5 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal
RegCSCondI11: is c=6 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow
RegCSCondI11: is c=6 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow
RegCSCondI11: is c=7 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd
CSCondI11: is RegCSCondI11 & f=0 { export RegCSCondI11; }
CSCondI11: is RegCSCondI11 & f=1 { temp:1 = ! RegCSCondI11; export temp; }
CSCondI11: is RegCSCondI11 & fv=0 { export RegCSCondI11; }
CSCondI11: is RegCSCondI11 & fv=1 { temp:1 = ! RegCSCondI11; export temp; }
CSCondI11Nullify: is c=0 & f=0 { }
CSCondI11Nullify: is c=0 & fv=0 { }
CSCondI11Nullify: is CSCondI11 [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = CSCondI11;
@@ -1643,13 +1644,13 @@ RegLogicCond: is c=2 & RT { tmp:1 = (RT & 0x80000000) != 0 ; export tmp; } # <,
RegLogicCond: is c=3 & RT { tmp:1 = ((RT & 0x80000000) != 0) || RT == 0 ; export tmp; } # <=, leftmost bit is 1 or all bits are zero
RegLogicCond: is c=7 & RT { tmp:1 = (RT & 0x1) == 0x1; export tmp; } # odd, rightmost bit is 1
LogicCond: is f=0 & RegLogicCond { tmp:1 = RegLogicCond; export tmp; } # non-inverted cases
LogicCond: is f=1 & RegLogicCond { tmp:1 = ! RegLogicCond; export tmp; } # inverted cases
LogicCond: is fv=0 & RegLogicCond { tmp:1 = RegLogicCond; export tmp; } # non-inverted cases
LogicCond: is fv=1 & RegLogicCond { tmp:1 = ! RegLogicCond; export tmp; } # inverted cases
LogicCondSym: RegLogicCondSym is RegLogicCondSym & f=0 { }
LogicCondSym: InvLogicCondSym is InvLogicCondSym & f=1 { }
LogicCondSym: RegLogicCondSym is RegLogicCondSym & fv=0 { }
LogicCondSym: InvLogicCondSym is InvLogicCondSym & fv=1 { }
LogicCondNullify: is c=0 & f=0 { }
LogicCondNullify: is c=0 & fv=0 { }
LogicCondNullify: is LogicCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ]
{
nullifyNextCond = LogicCond;
@@ -1661,45 +1662,45 @@ LogicCondNullify: is LogicCond [ nullifyEnable = 1; globalset(inst_next, nullify
# Table 5-11 on page 5-22
# The shifted form for byte doesn't shift, as byte addressing is single byte aligned
indexedByteAccessCmplt: is u=0 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(RX); export offset; } # none
indexedByteAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export offset; } # M, modify, post inc by RX
indexedByteAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(RX); export offset; } # S, shift left by 2
indexedByteAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX); export offset; } # SM, shift and modify
indexedByteAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none
indexedByteAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX
indexedByteAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # S, shift left by 2
indexedByteAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX); export off; } # SM, shift and modify
# The shifted form for halfword shifts by 2 bytes, since that is the size of a halfword
indexedHalfwordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(RX); export offset; } # none
indexedHalfwordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export offset; } # M, modify, post inc by RX
indexedHalfwordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext((RX << 1)); export offset; } # S, shift left by 1
indexedHalfwordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 1); export offset; } # SM, shift and modify
indexedHalfwordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none
indexedHalfwordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX
indexedHalfwordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 1)); export off; } # S, shift left by 1
indexedHalfwordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 1); export off; } # SM, shift and modify
# The shifted form for words shifts by 2 (x4), since words are aligned on 4 and increment by 4
indexedWordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(RX); export offset; } # none
indexedWordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export offset; } # M, modify, post inc by RX
indexedWordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext((RX << 2)); export offset; } # S, shift left by 2
indexedWordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 2); export offset; } # SM, shift and modify
indexedWordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none
indexedWordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX
indexedWordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 2)); export off; } # S, shift left by 2
indexedWordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 2); export off; } # SM, shift and modify
# same as above, but shifts by 3 bits. Used for the LDCWX instruction
indexedDoublewordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(RX); export offset; } # none
indexedDoublewordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export offset; } # M, modify, post inc by RX
indexedDoublewordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext((RX << 3)); export offset; } # S, shift left by 3 NOTE YES THIS IS 3
indexedDoublewordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 3); export offset; } # SM, shift and modify
indexedDoublewordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none
indexedDoublewordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX
indexedDoublewordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 3)); export off; } # S, shift left by 3 NOTE YES THIS IS 3
indexedDoublewordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 3); export off; } # SM, shift and modify
# Table 5-12 on Page 5-24
# these are for loads, e.g. ldws
shortDispCmplt: is m=0 & highlse5 & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(highlse5); export offset; } # no modification
shortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & highlse5 { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(highlse5); export offset; } # modify after
shortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & highlse5 { lse = sext(highlse5); offset:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export offset; } # modify before
shortDispCmplt: is m=0 & highlse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(highlse5); export off; } # no modification
shortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & highlse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(highlse5); export off; } # modify after
shortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & highlse5 { local lse = sext(highlse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before
# short displacement for stores, e.g. stws
storeShortDispCmplt: is m=0 & lse5 & SPCBASE { offset:$(ADDRSIZE) = SPCBASE + sext(lse5); export offset; } # no modification
storeShortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & lse5 { offset:$(ADDRSIZE) = SPCBASE; RB = RB + sext(lse5); export offset; } # modify after
storeShortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & lse5 { lse = sext(lse5); offset:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export offset; } # modify before
storeShortDispCmplt: is m=0 & lse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # no modification
storeShortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(lse5); export off; } # modify after
storeShortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & lse5 { local lse = sext(lse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before
# Table 5-13 on page 5-26
storeBytesShortCmplt: is u=0 & m=0 & SPCBASE & lse5 { offset:$(ADDRSIZE) = SPCBASE + sext(lse5); export offset; } # none / beginning, don't modify base register
storeBytesShortCmplt: ",BM" is u=0 & m=1 & SPCBASE & RR & lse5 { offset:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export offset; } # beginning, modify base register
storeBytesShortCmplt: ",E" is u=1 & m=0 & SPCBASE & lse5 { offset:$(ADDRSIZE) = SPCBASE + sext(lse5); export offset; } # ending, don't modify
storeBytesShortCmplt: ",EM" is u=1 & m=1 & SPCBASE & RR & lse5 { offset:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export offset; } # ending, modify
storeBytesShortCmplt: is u=0 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # none / beginning, don't modify base register
storeBytesShortCmplt: ",BM" is u=0 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # beginning, modify base register
storeBytesShortCmplt: ",E" is u=1 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # ending, don't modify
storeBytesShortCmplt: ",EM" is u=1 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # ending, modify
# u fixed at 0, Table 5-11 on page 5-22, for LPA and related system level opcodes
sysCmplt: is m=0 { }
Ghidra/Processors/PA-RISC/data/languages/pa-riscInstructions.sinc
+80 -80
View File
@@ -39,18 +39,18 @@ with : phase=1 {
}
:LDW^",M" OFF_BASE_14,R1dst is opfam=0x13 & OFF_BASE_14 & R1dst & RB & SPCBASE & lse14 {
offset:$(ADDRSIZE) = 0;
off:$(ADDRSIZE) = 0;
if (lse14 s>= 0x0) goto <IGNOREIMM>;
offset = sext(lse14);
off = sext(lse14);
<IGNOREIMM>
addr:$(ADDRSIZE) = SPCBASE + offset;
addr:$(ADDRSIZE) = SPCBASE + off;
RB = RB + lse14;
R1dst = zext( *[ram]:4 addr );
}
:STW^",M" R1,OFF_BASE_14 is opfam=0x1B & OFF_BASE_14 & R1 & RB & SPCBASE & lse14 {
addr:$(ADDRSIZE) = SPCBASE;
imm = sext(lse14);
local imm = sext(lse14);
if (imm s>= 0x0) goto <IGNOREIMM>;
addr = addr + imm;
<IGNOREIMM>
@@ -145,9 +145,9 @@ with : phase=1 {
# get the address, which is most likely not word aligned
addr:$(ADDRSIZE) = storeBytesShortCmplt;
# figure out how many bytes need to be written
numBytes = 4 - (addr & 0x3);
local numBytes = 4 - (addr & 0x3);
# this is the address where we stop (one byte past the last address to which we write)
finalAddr = addr + numBytes;
local finalAddr = addr + numBytes;
# copy the contents of RR
data:$(REGSIZE) = RR >> ((4 - numBytes) * 8);
# use a for loop to write out the 1,2,3, or 4 bytes
@@ -165,11 +165,11 @@ with : phase=1 {
# get the address, which is most likely not word aligned
addr:$(ADDRSIZE) = storeBytesShortCmplt;
# figure out how many bytes need to be written
numBytes = (addr & 0x3);
local numBytes = (addr & 0x3);
# now make a word aligned address
addr = addr & 0x3;
# this is the address where we stop (one byte past the last address to which we write)
finalAddr = addr + numBytes;
local finalAddr = addr + numBytes;
# copy the contents of RR
data:$(REGSIZE) = RR >> ((4 - numBytes) * 8);
@@ -216,7 +216,7 @@ with : phase=1 {
# unconditional immediate calls
################################################################################
# non-nullifying unconditional immediate call
:B^",L"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifyForBranch & n=0 & branchTarget3W $(COMMON)
:B^",L"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifyForBranch & n=0 & branchTarget3W & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -232,7 +232,7 @@ with : phase=1 {
# nullifying unconditional immediate call
# special case that doesn't need the deferral mechanism
:B^",L"^nullifySymForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifySymForBranch & n=1 & branchTarget3W $(COMMON)
:B^",L"^nullifySymForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON)
{
R2dst = inst_start+8;
call branchTarget3W;
@@ -244,7 +244,7 @@ with : phase=1 {
# By having a second op for it, we can use a goto and prevent analysis tools from thinking this is a legitimate subroutine call
################################################################################
# non-nullifying unconditional immediate branch (no link)
:B^nullifyForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifyForBranch & n=0 & branchTarget3W $(COMMON)
:B^nullifyForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifyForBranch & n=0 & branchTarget3W & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -261,7 +261,7 @@ with : phase=1 {
# nullifying unconditional immediate branch (no link)
# This is a special case, as we just do the branch and don't use
# our defered branching mechanism
:B^nullifySymForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifySymForBranch & n=1 & branchTarget3W $(COMMON)
:B^nullifySymForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON)
{
goto branchTarget3W;
}
@@ -269,7 +269,7 @@ with : phase=1 {
################################################################################
# conditional immediate branches - comparison with registers
################################################################################
:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond $(COMMON)
:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -282,7 +282,7 @@ with : phase=1 {
branchExecuted = 1;
}
:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond $(COMMON)
:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -296,7 +296,7 @@ with : phase=1 {
nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );
}
:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond $(COMMON)
:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -309,7 +309,7 @@ with : phase=1 {
branchExecuted = 1;
}
:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond $(COMMON)
:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -326,7 +326,7 @@ with : phase=1 {
################################################################################
# conditional immediate branches -- comparison with immediates
################################################################################
:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 $(COMMON)
:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -339,7 +339,7 @@ with : phase=1 {
branchExecuted = 1;
}
:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 $(COMMON)
:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -353,7 +353,7 @@ with : phase=1 {
nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) );
}
:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 $(COMMON)
:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -366,7 +366,7 @@ with : phase=1 {
branchExecuted = 1;
}
:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 $(COMMON)
:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -384,7 +384,7 @@ with : phase=1 {
# unconditional indirect calls & branches
################################################################################
# IP relative unconditional indirect call
:BLR^nullifyForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifyForBranch & RR & IPRelativeIndexedTarget & n=0 $(COMMON)
:BLR^nullifyForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifyForBranch & RR & IPRelativeIndexedTarget & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -399,14 +399,14 @@ with : phase=1 {
}
# IP relative unconditional indirect call
:BLR^nullifySymForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifySymForBranch & RR & IPRelativeIndexedTarget & n=1 $(COMMON)
:BLR^nullifySymForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifySymForBranch & RR & IPRelativeIndexedTarget & n=1 & $(COMMON)
{
R2dst = inst_start+8;
call [branchIndDest];
}
# vectored (offset register plus index register) unconditional indirect branch
:BV^nullifyForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & RX & IndexedTarget & bit0=0 & n=0 $(COMMON)
:BV^nullifyForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & RX & IndexedTarget & bit0=0 & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -420,14 +420,14 @@ with : phase=1 {
}
# vectored (offset register plus index register) unconditional indirect branch
:BV^nullifySymForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifySymForBranch & RX & IndexedTarget & bit0=0 & n=1 $(COMMON)
:BV^nullifySymForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifySymForBranch & RX & IndexedTarget & bit0=0 & n=1 & $(COMMON)
{
goto [branchIndDest];
}
# this is the idiom for return from subroutine
# currently we pull it out so we don't print out the R0, but we could modify this to do a return...
:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=0 $(COMMON)
:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -444,7 +444,7 @@ with : phase=1 {
# this is the idiom for return from subroutine
# currently we pull it out so we don't print out the R0, but we could modify this to do a return...
:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=1 $(COMMON)
:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=1 & $(COMMON)
{
return [branchIndDest];
}
@@ -453,7 +453,7 @@ with : phase=1 {
#### MOVB
:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 $(COMMON)
:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -469,7 +469,7 @@ with : phase=1 {
branchExecuted = 1;
}
:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 $(COMMON)
:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -490,7 +490,7 @@ with : phase=1 {
#### MOVIB
:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 $(COMMON)
:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -506,7 +506,7 @@ with : phase=1 {
branchCond = DepCond;
}
:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 $(COMMON)
:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -524,7 +524,7 @@ with : phase=1 {
}
###########################
:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 $(COMMON)
:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -539,7 +539,7 @@ with : phase=1 {
R2dst = R1 + R2;
}
:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegAddCond & RegAddCondSym & n=1 $(COMMON)
:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegAddCond & RegAddCondSym & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -557,7 +557,7 @@ with : phase=1 {
}
###########################
:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 $(COMMON)
:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -572,7 +572,7 @@ with : phase=1 {
R2dst = R1 + R2;
}
:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondSym & RegAddCond & n=1 $(COMMON)
:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondSym & RegAddCond & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -589,7 +589,7 @@ with : phase=1 {
}
###########################
:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 $(COMMON)
:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -604,7 +604,7 @@ with : phase=1 {
R2dst = R2 + sext(highlse5);
}
:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 $(COMMON)
:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -620,7 +620,7 @@ with : phase=1 {
R2dst = R2 + sext(highlse5);
}
:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 $(COMMON)
:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -635,7 +635,7 @@ with : phase=1 {
R2dst = R2 + sext(highlse5);
}
:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 $(COMMON)
:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -652,7 +652,7 @@ with : phase=1 {
}
#######################################
:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & R1 & BVBCond & SEDCondSym & SAR & n=0 $(COMMON)
:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & R1 & BVBCond & SEDCondSym & SAR & n=0 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -665,7 +665,7 @@ with : phase=1 {
branchExecuted = 1;
}
:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & displacement2W & R1 & BVBCond & SEDCondSym & SAR & n=1 $(COMMON)
:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & displacement2W & R1 & BVBCond & SEDCondSym & SAR & n=1 & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -680,7 +680,7 @@ with : phase=1 {
}
#######################################
:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=0 & bboffset $(COMMON)
:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=0 & bboffset & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -693,7 +693,7 @@ with : phase=1 {
branchExecuted = 1;
}
:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & displacement2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=1 & bboffset $(COMMON)
:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & displacement2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=1 & bboffset & $(COMMON)
[ branchEnable = 1;
globalset(inst_next, branchEnable);
branchType = 2; # conditional imm branch
@@ -713,7 +713,7 @@ define pcodeop changePrivLevel;
define pcodeop changeSpace;
define pcodeop getCurrentSpace;
:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=0 $(COMMON)
:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -728,13 +728,13 @@ define pcodeop getCurrentSpace;
branchExecuted = 1;
}
:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=1 $(COMMON)
:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=1 & $(COMMON)
{
iasq_front = SR3bit; # set the space ID to the new space ID
goto [externalTarget];
}
:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=0 $(COMMON)
:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -751,7 +751,7 @@ define pcodeop getCurrentSpace;
branchExecuted = 1;
}
:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=1 $(COMMON)
:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=1 & $(COMMON)
{
r31 = inst_next+4; # store the link/return address
sr0 = iasq_front; # store the link/return space ID
@@ -759,7 +759,7 @@ define pcodeop getCurrentSpace;
call [externalTarget];
}
:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=0 $(COMMON)
:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=0 & $(COMMON)
[
branchEnable = 1;
globalset(inst_next, branchEnable);
@@ -773,7 +773,7 @@ define pcodeop getCurrentSpace;
branchExecuted = 1;
}
:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=1 $(COMMON)
:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=1 & $(COMMON)
{
R2dst = changePrivLevel();
goto [branchTarget3W];
@@ -811,7 +811,7 @@ define pcodeop trap;
}
:ADD^",C"^AddCondSym R1,R2,RT is opfam=0x02 & op=0x1C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify {
partialSum = R2 + zext(pswCB);
local partialSum = R2 + zext(pswCB);
pswCB = carry(partialSum, R1);
RT = partialSum + R1;
build AddCondNullify;
@@ -819,7 +819,7 @@ define pcodeop trap;
# TODO This may need some work
:ADD^",CO"^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify {
partialSum = R2 + zext(pswCB);
local partialSum = R2 + zext(pswCB);
partialCarry:1 = carry(R2, zext(pswCB));
partialOverflow:1 = scarry(R2, zext(pswCB));
takeTrap:1 = partialOverflow == 0x1:1;
@@ -838,20 +838,20 @@ define pcodeop trap;
}
:SH1ADD^AddCondSym R1,R2,RT is opfam=0x02 & op=0x19 & m=0 & R1 & R2 & RT & AddCond & AddCondSym & AddCondNullify {
shiftedR1 = R1 << 1;
local shiftedR1 = R1 << 1;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH1ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x29 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 1;
local shiftedR1 = R1 << 1;
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH1ADDO^SEDCondSym R1,R2,RT is opfam=0x02 & op=0x39 & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym {
shiftedR1 = R1 << 1;
local shiftedR1 = R1 << 1;
if (scarry(shiftedR1, R2)) goto <TRAP>;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
@@ -863,20 +863,20 @@ define pcodeop trap;
}
:SH2ADD^SEDCondSym R1,R2,RT is opfam=0x02 & op=0x1A & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym {
shiftedR1 = R1 << 2;
local shiftedR1 = R1 << 2;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH2ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x2A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 2;
local shiftedR1 = R1 << 2;
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH2ADDO^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 2;
local shiftedR1 = R1 << 2;
if (scarry(shiftedR1, R2)) goto <TRAP>;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
@@ -888,20 +888,20 @@ define pcodeop trap;
}
:SH3ADD^AddCondSym R1,R2,RT is opfam=0x02 & op=0x1B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 3;
local shiftedR1 = R1 << 3;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH3ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x2B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 3;
local shiftedR1 = R1 << 3;
RT = shiftedR1 + R2;
build AddCondNullify;
}
:SH3ADDO^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym {
shiftedR1 = R1 << 3;
local shiftedR1 = R1 << 3;
if (scarry(shiftedR1, R2)) goto <TRAP>;
pswCB = carry(shiftedR1,R2);
RT = shiftedR1 + R2;
@@ -975,7 +975,7 @@ define pcodeop trap;
# R1 is partial remainder, R2 is denominator, RT is updated partial remainder
:DS^CSCondSym R1,R2,RT is opfam=0x02 & op=0x11 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify {
origR2 = R2;
local origR2 = R2;
left:$(REGSIZE) = (R1 << 1) | zext(pswCB);
if (pswV) goto <MINUS>;
right:$(REGSIZE) = R2;
@@ -1004,12 +1004,12 @@ define pcodeop trap;
}
# COPY is a pseudo-op using OR to move values between registers
:COPY R1,RT is opfam=0x02 & op=0x09 & m=0 & R1 & reg2=0 & RT & c=0 & f=0 {
:COPY R1,RT is opfam=0x02 & op=0x09 & m=0 & R1 & reg2=0 & RT & c=0 & fv=0 {
RT = R1;
}
# nop is a pseudo-op for OR R0,R0, which is one way to make a nop
:NOP is opfam=0x02 & op=0x09 & m=0 & reg1=0 & reg2=0 & t=0 & c=0 & f=0 { } # intentionally left blank
:NOP is opfam=0x02 & op=0x09 & m=0 & reg1=0 & reg2=0 & t=0 & c=0 & fv=0 { } # intentionally left blank
:OR^LogicCondSym R1,R2,RT is opfam=0x02 & op=0x09 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify {
RT = R1 | R2;
@@ -1145,7 +1145,7 @@ define pcodeop trap;
# extract unsigned using SAR
:EXTRW",U"^SEDCondSym R2,SAR,shiftCLen,R1dst is opfam=0x34 & bits59=0 & subop1012=4 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR {
value = R2 >> (31-SAR);
local value = R2 >> (31-SAR);
mask:4 = 0xffffffff >> (32 - shiftCLen);
nullifyCondResult = value & mask;
R1dst = nullifyCondResult;
@@ -1155,7 +1155,7 @@ define pcodeop trap;
# extract signed using SAR
:EXTRW",S"^SEDCondSym R2,SAR,shiftCLen,R1dst is opfam=0x34 & bits59=0 & subop1012=5 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR {
value = R2 s>> (31-SAR);
local value = R2 s>> (31-SAR);
value = value << (32 - shiftCLen);
value = value s>> (32 - shiftCLen);
nullifyCondResult = value;
@@ -1165,7 +1165,7 @@ define pcodeop trap;
# extract unsigned using immediate
:EXTRW^",U"^SEDCondSym R2,cp,shiftCLen,R1dst is opfam=0x34 & subop1012=6 & cp & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & shiftC {
value = R2 >> shiftC;
local value = R2 >> shiftC;
mask:4 = 0xffffffff >> (32-shiftCLen);
nullifyCondResult = value & mask;
R1dst = nullifyCondResult;
@@ -1175,7 +1175,7 @@ define pcodeop trap;
# extract signed using immediate
:EXTRW^",S"^SEDCondSym R2,cp,shiftCLen,R1dst is opfam=0x34 & subop1012=7 & cp & R2 & shiftC & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify {
value = R2 s>> shiftC;
local value = R2 s>> shiftC;
value = value << (32 - shiftCLen);
value = value s>> (32 - shiftCLen);
nullifyCondResult = value;
@@ -1186,10 +1186,10 @@ define pcodeop trap;
# non-zeroing SAR version (VDEP)
:DEPW^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=1 & R1 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & SAR {
mask:4 = 0xffffffff >> (32-shiftCLen);
value = R1 & mask;
local value = R1 & mask;
value = value << (31-SAR);
mask = mask << (31-SAR);
result = R2 & ~mask;
local result = R2 & ~mask;
result = result | value;
R2dst = result;
nullifyCondResult = result;
@@ -1200,10 +1200,10 @@ define pcodeop trap;
# non-zeroing constant version (DEP)
:DEPW^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=3 & shiftC & shiftCLen & R1 & R2 & R2dst & DepCondNullify & SEDCondSym & cp {
mask:4 = 0xffffffff >> (32-shiftCLen);
value = R1 & mask;
local value = R1 & mask;
value = value << cp;
mask = mask << cp;
result = R2 & ~mask;
local result = R2 & ~mask;
result = result | value;
R2dst = result;
nullifyCondResult = result;
@@ -1215,10 +1215,10 @@ define pcodeop trap;
mask:4 = 0xffffffff >> (32 - shiftCLen);
depbits:4 = sext(highlse5);
depbits = sext(depbits);
value = depbits & mask;
local value = depbits & mask;
value = value << (31-SAR);
mask = mask << (31-SAR);
result = R2 & ~mask;
local result = R2 & ~mask;
result = result | value;
R2dst = result;
nullifyCondResult = result;
@@ -1229,10 +1229,10 @@ define pcodeop trap;
:DEPWI^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=7 & shiftC & highlse5 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp {
mask:4 = 0xffffffff >> (32-shiftCLen);
depbits:4 = sext(highlse5);
value = depbits & mask;
local value = depbits & mask;
value = value << cp;
mask = mask << cp;
result = R2 & ~mask;
local result = R2 & ~mask;
result = result | value;
R2dst = result;
nullifyCondResult = result;
@@ -1242,7 +1242,7 @@ define pcodeop trap;
# DEPW,Z SAR version (ZVDEP)
:DEPW",Z"^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=0 & R1 & shiftCLen & R2 & R2dst & DepCondNullify & SEDCondSym & SAR {
mask:4 = 0xffffffff >> (32-shiftCLen);
value = R1 & mask;
local value = R1 & mask;
value = value << (31-SAR);
R2dst = value;
nullifyCondResult = value;
@@ -1252,7 +1252,7 @@ define pcodeop trap;
# DEPW,Z constant version (ZDEP)
:DEPW^",Z"^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=2 & shiftC & R2 & R2dst & shiftCLen & R1 & DepCondNullify & SEDCondSym & cp {
mask:4 = 0xffffffff >> (32-shiftCLen);
value = R1 & mask;
local value = R1 & mask;
value = value << cp;
R2dst = value;
nullifyCondResult = value;
@@ -1263,7 +1263,7 @@ define pcodeop trap;
:DEPWI",Z"^SEDCondSym highlse5,SAR,shiftCLen,R2dst is opfam=0x35 & SAR & bits59=0 & subop1012=4 & shiftCLen & highlse5 & R2dst & DepCondNullify & SEDCondSym {
mask:4 = 0xffffffff >> (32-shiftCLen);
depbits:4 = sext(highlse5);
value = depbits & mask;
local value = depbits & mask;
value = value << (31-SAR);
R2dst = value;
nullifyCondResult = value;
@@ -1274,7 +1274,7 @@ define pcodeop trap;
:DEPWI",Z"^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=6 & shiftC & highlse5 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp {
mask:4 = 0xffffffff >> (32-shiftCLen);
depbits:4 = sext(highlse5);
value = depbits & mask;
local value = depbits & mask;
value = value << cp;
nullifyCondResult = value;
R2dst = value;
@@ -1300,7 +1300,7 @@ define pcodeop break;
iasq_front = cr17;
upperBits:8 = zext(iasq_front);
lowerBits:8 = zext(iaoq_front);
returnAddr = (upperBits << 32) | lowerBits;
local returnAddr = (upperBits << 32) | lowerBits;
goto [returnAddr];
}
@@ -1880,7 +1880,7 @@ define pcodeop diag;
compareBit = result;
}
:FTEST^fptest is opfam=0x0C & fpclass=2 & fpsub=1 & fptest $(COMMON)
:FTEST^fptest is opfam=0x0C & fpclass=2 & fpsub=1 & fptest & $(COMMON)
[
nullifyEnable = 1;
globalset(inst_next, nullifyEnable);
Ghidra/Processors/Z80/certification.manifest
+1 -1
View File
@@ -2,7 +2,7 @@
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/languages/z180.pspec||GHIDRA||||END|
data/languages/z180.slaspec||GHIDRA||reviewed||END|
data/languages/z180.slaspec||GHIDRA||||END|
data/languages/z182.pspec||GHIDRA||||END|
data/languages/z80.cspec||GHIDRA||||END|
data/languages/z80.ldefs||GHIDRA||||END|
Ghidra/Processors/Z80/data/languages/z180.slaspec
+1 -1
View File
@@ -1,3 +1,3 @@
@define Z180
@define Z180 ""
@include "z80.slaspec"