diff --git a/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/guest/DBTraceGuestPlatformMappedMemory.java b/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/guest/DBTraceGuestPlatformMappedMemory.java
index 713c95615b..ea70425ed2 100644
--- a/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/guest/DBTraceGuestPlatformMappedMemory.java
+++ b/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/guest/DBTraceGuestPlatformMappedMemory.java
@@ -34,7 +34,6 @@ import ghidra.trace.database.memory.DBTraceMemoryManager;
 import ghidra.trace.database.memory.DBTraceMemorySpace;
 import ghidra.util.MathUtilities;
 import ghidra.util.exception.CancelledException;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 /**
@@ -305,31 +304,31 @@ public class DBTraceGuestPlatformMappedMemory implements Memory {
 	@Override
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
 			throws LockException, MemoryBlockException, MemoryConflictException,
-			AddressOverflowException, NotFoundException {
+			AddressOverflowException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public void split(MemoryBlock block, Address addr)
-			throws MemoryBlockException, LockException, NotFoundException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToUninitialized(MemoryBlock itializedBlock)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
diff --git a/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/program/AbstractDBTraceProgramViewMemory.java b/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/program/AbstractDBTraceProgramViewMemory.java
index 762fc1e884..cb25bf57d3 100644
--- a/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/program/AbstractDBTraceProgramViewMemory.java
+++ b/Ghidra/Debug/Framework-TraceModeling/src/main/java/ghidra/trace/database/program/AbstractDBTraceProgramViewMemory.java
@@ -33,7 +33,6 @@ import ghidra.trace.util.MemoryAdapter;
 import ghidra.util.LockHold;
 import ghidra.util.MathUtilities;
 import ghidra.util.exception.CancelledException;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 public abstract class AbstractDBTraceProgramViewMemory
@@ -206,31 +205,31 @@ public abstract class AbstractDBTraceProgramViewMemory
 	@Override
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
 			throws LockException, MemoryBlockException, MemoryConflictException,
-			AddressOverflowException, NotFoundException {
+			AddressOverflowException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public void split(MemoryBlock block, Address addr)
-			throws MemoryBlockException, LockException, NotFoundException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToUninitialized(MemoryBlock itializedBlock)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/cmd/memory/MoveBlockTask.java b/Ghidra/Features/Base/src/main/java/ghidra/app/cmd/memory/MoveBlockTask.java
index fc6837096e..0a488d5cd4 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/cmd/memory/MoveBlockTask.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/cmd/memory/MoveBlockTask.java
@@ -20,7 +20,6 @@ import ghidra.program.model.listing.Program;
 import ghidra.program.model.mem.*;
 import ghidra.program.util.ProgramTask;
 import ghidra.util.Msg;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.exception.RollbackException;
 import ghidra.util.task.TaskMonitor;
 
@@ -80,10 +79,6 @@ public class MoveBlockTask extends ProgramTask {
 			statusMessage = "Insufficient memory to complete operation";
 			cause = e;
 		}
-		catch (NotFoundException e) {
-			statusMessage = "Memory block not found";
-			cause = e;
-		}
 		catch (MemoryConflictException | MemoryBlockException | IllegalArgumentException e) {
 			statusMessage = e.getMessage();
 			cause = e;
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/analysis/GolangSymbolAnalyzer.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/analysis/GolangSymbolAnalyzer.java
index 2d31c9333e..2ccf428c5c 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/analysis/GolangSymbolAnalyzer.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/analysis/GolangSymbolAnalyzer.java
@@ -693,7 +693,7 @@ public class GolangSymbolAnalyzer extends AbstractAnalyzer {
 					memBlk = memory.getBlock(afterFlag);
 					memBlk.setName(memBlk.getName().replaceFirst("(\\.split)+$", ".part2"));
 				}
-				catch (MemoryBlockException | LockException | NotFoundException e) {
+				catch (MemoryBlockException | LockException e) {
 					Msg.error(this, "Failed to fixup runtime.writeBarrier flag", e);
 				}
 			}
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/memory/MemoryMapManager.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/memory/MemoryMapManager.java
index 61f548bb48..42b7a2d70f 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/memory/MemoryMapManager.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/memory/MemoryMapManager.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -27,7 +27,8 @@ import ghidra.program.model.address.*;
 import ghidra.program.model.listing.*;
 import ghidra.program.model.mem.*;
 import ghidra.util.Msg;
-import ghidra.util.exception.*;
+import ghidra.util.exception.DuplicateNameException;
+import ghidra.util.exception.RollbackException;
 
 /**
  * Helper class to make changes to memory blocks.
@@ -270,10 +271,6 @@ class MemoryMapManager {
 				msg = e.getMessage();
 				return false;
 			}
-			catch (NotFoundException e) {
-				msg = e.getMessage();
-				return false;
-			}
 			catch (LockException e) {
 				msg = e.getMessage();
 				return false;
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/debug/GenerateOldLanguagePlugin.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/debug/GenerateOldLanguagePlugin.java
index b0c600bbf2..bc68a1f221 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/debug/GenerateOldLanguagePlugin.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/debug/GenerateOldLanguagePlugin.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -43,6 +43,7 @@ import ghidra.framework.Application;
 import ghidra.framework.main.ApplicationLevelPlugin;
 import ghidra.framework.plugintool.*;
 import ghidra.framework.plugintool.util.PluginStatus;
+import ghidra.program.database.ProgramDB;
 import ghidra.program.model.address.AddressSpace;
 import ghidra.program.model.lang.*;
 import ghidra.program.model.listing.IncompatibleLanguageException;
@@ -50,6 +51,7 @@ import ghidra.program.util.*;
 import ghidra.util.Msg;
 import ghidra.util.exception.AssertException;
 import ghidra.util.filechooser.ExtensionFileFilter;
+import ghidra.util.task.TaskMonitor;
 import ghidra.util.xml.GenericXMLOutputter;
 
 //@formatter:off
@@ -395,8 +397,7 @@ public class GenerateOldLanguagePlugin extends Plugin implements ApplicationLeve
 			Register oldCtx = oldLang.getContextBaseRegister();
 			Register newCtx = newLang.getContextBaseRegister();
 			boolean contextWarning = false;
-			if (oldCtx != Register.NO_CONTEXT &&
-				defaultTrans.isValueTranslationRequired(oldCtx)) {
+			if (oldCtx != Register.NO_CONTEXT && defaultTrans.isValueTranslationRequired(oldCtx)) {
 				contextWarning = true;
 			}
 			else if (oldCtx == Register.NO_CONTEXT && newCtx != Register.NO_CONTEXT) {
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/AbstractProgramLoader.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/AbstractProgramLoader.java
index 6417e554e9..0fc5bcae16 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/AbstractProgramLoader.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/AbstractProgramLoader.java
@@ -325,9 +325,8 @@ public abstract class AbstractProgramLoader implements Loader {
 			prog.setExecutableFormat(executableFormatName);
 		}
 		FSRL fsrl = provider.getFSRL();
-		String md5 = (fsrl != null && fsrl.getMD5() != null)
-				? fsrl.getMD5()
-				: computeBinaryMD5(provider);
+		String md5 =
+			(fsrl != null && fsrl.getMD5() != null) ? fsrl.getMD5() : computeBinaryMD5(provider);
 		if (fsrl != null) {
 			if (fsrl.getMD5() == null) {
 				fsrl = fsrl.withMD5(md5);
@@ -470,6 +469,19 @@ public abstract class AbstractProgramLoader implements Loader {
 		return DefaultLanguageService.getLanguageService();
 	}
 
+	private AddressSetView getProcessorDefinedMemoryBlockAddresses(Program program) {
+		AddressSet blockAddrSet = new AddressSet();
+		Memory memory = program.getMemory();
+		Language language = program.getLanguage();
+		for (MemoryBlockDefinition defaultMemoryBlockDef : language.getDefaultMemoryBlocks()) {
+			MemoryBlock block = memory.getBlock(defaultMemoryBlockDef.getBlockName());
+			if (block != null) {
+				blockAddrSet.add(block.getAddressRange());
+			}
+		}
+		return blockAddrSet;
+	}
+
 	private void applyProcessorLabels(List<Option> options, Program program) {
 		int id = program.startTransaction("Finalize load");
 		try {
@@ -482,15 +494,25 @@ public abstract class AbstractProgramLoader implements Loader {
 					createSymbol(program, reg.getName(), addr, null, false, true, true);
 				}
 			}
-			// optionally create default symbols defined by pspec
-			if (shouldApplyProcessorLabels(options)) {
-				boolean anchorSymbols = shouldAnchorSymbols(options);
-				List<AddressLabelInfo> labels = lang.getDefaultSymbols();
-				for (AddressLabelInfo info : labels) {
-					createSymbol(program, info.getLabel(), info.getAddress(), info.getDescription(), info.isEntry(),
-						info.isPrimary(), anchorSymbols);
+
+			// NOTE: pspec defined labels should always be defined if they correspond to a memory
+			// block defined by the pspec.
+			boolean applyAllProcessorLabels = shouldApplyProcessorLabels(options);
+			AddressSetView pspecDefinedBlockSet = getProcessorDefinedMemoryBlockAddresses(program);
+			boolean anchorSymbols = shouldAnchorSymbols(options);
+			List<AddressLabelInfo> labels = lang.getDefaultSymbols();
+			for (AddressLabelInfo info : labels) {
+				Address addr = info.getAddress();
+				boolean isRequiredLabel = pspecDefinedBlockSet.contains(addr);
+				if (isRequiredLabel || applyAllProcessorLabels) {
+					// NOTE: Required labels contained within a pspec-defined memory block do not 
+					// need to be pinned/anchored
+					boolean anchor = !isRequiredLabel && anchorSymbols;
+					createSymbol(program, info.getLabel(), info.getAddress(), info.getDescription(),
+						info.isEntry(), info.isPrimary(), anchor);
 				}
 			}
+
 			GhidraProgramUtilities.resetAnalysisFlags(program);
 		}
 		finally {
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/NeLoader.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/NeLoader.java
index d56545be40..a06295188b 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/NeLoader.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/opinion/NeLoader.java
@@ -269,7 +269,7 @@ public class NeLoader extends AbstractOrdinalSupportLoader {
 						try {
 							block = program.getMemory().join(block, zeroBlock); // expand
 						}
-						catch (MemoryBlockException | LockException | NotFoundException e) {
+						catch (MemoryBlockException | LockException e) {
 							throw new IOException(e);
 						}
 					}
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/program/util/MemoryDiff.java b/Ghidra/Features/Base/src/main/java/ghidra/program/util/MemoryDiff.java
index 3b7c32b7a1..b6f836eeba 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/program/util/MemoryDiff.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/program/util/MemoryDiff.java
@@ -23,7 +23,6 @@ import ghidra.program.model.listing.Program;
 import ghidra.program.model.mem.*;
 import ghidra.util.Msg;
 import ghidra.util.SystemUtilities;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 /**
@@ -297,9 +296,6 @@ public class MemoryDiff {
 				catch (LockException e) {
 					Msg.error(this, "Unexpected Exception: " + e.getMessage(), e);
 				}
-				catch (NotFoundException e) {
-					Msg.error(this, "Unexpected Exception: " + e.getMessage(), e);
-				}
 				catch (AddressOutOfBoundsException e) {
 					Msg.error(this, "Unexpected Exception: " + e.getMessage(), e);
 				}
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/program/util/SymbolicPropogator.java b/Ghidra/Features/Base/src/main/java/ghidra/program/util/SymbolicPropogator.java
index f73db0bd27..357f62d1c8 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/program/util/SymbolicPropogator.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/program/util/SymbolicPropogator.java
@@ -879,10 +879,13 @@ public class SymbolicPropogator {
 			try {
 				switch (ptype) {
 					case PcodeOp.COPY:
-						if (in[0].isAddress() &&
-							!in[0].getAddress().getAddressSpace().hasMappedRegisters()) {
-							makeReference(vContext, instruction,  Reference.MNEMONIC, in[0],
-								null, RefType.READ, ptype, true, monitor);
+						if (in[0].isAddress()) {
+							AddressSpace addressSpace = in[0].getAddress().getAddressSpace();
+							// if not address mapped, or no register defined there
+							if (!addressSpace.hasMappedRegisters() || program.getRegister(in[0]) == null) {
+							    makeReference(vContext, instruction,  Reference.MNEMONIC, in[0],
+								    null, RefType.READ, ptype, true, monitor);
+							}
 						}
 						vContext.copy(out, in[0], mustClearAll, evaluator);
 						break;
diff --git a/Ghidra/Features/Base/src/test/java/ghidra/app/plugin/core/checksums/MyTestMemory.java b/Ghidra/Features/Base/src/test/java/ghidra/app/plugin/core/checksums/MyTestMemory.java
index 8720c24068..e8e98c6ae6 100644
--- a/Ghidra/Features/Base/src/test/java/ghidra/app/plugin/core/checksums/MyTestMemory.java
+++ b/Ghidra/Features/Base/src/test/java/ghidra/app/plugin/core/checksums/MyTestMemory.java
@@ -25,7 +25,6 @@ import ghidra.program.model.address.*;
 import ghidra.program.model.listing.Program;
 import ghidra.program.model.mem.*;
 import ghidra.util.exception.CancelledException;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 public class MyTestMemory extends AddressSet implements Memory {
@@ -153,30 +152,30 @@ public class MyTestMemory extends AddressSet implements Memory {
 
 	@Override
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
-			throws MemoryConflictException, AddressOverflowException, NotFoundException {
+			throws MemoryConflictException, AddressOverflowException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
-	public void split(MemoryBlock block, Address addr) throws NotFoundException {
+	public void split(MemoryBlock block, Address addr) {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws MemoryBlockException, NotFoundException {
+			throws MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws MemoryBlockException, NotFoundException {
+			throws MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToUninitialized(MemoryBlock initializedBlock)
-			throws MemoryBlockException, NotFoundException {
+			throws MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
diff --git a/Ghidra/Features/FileFormats/src/main/java/ghidra/file/formats/dump/DumpFileLoader.java b/Ghidra/Features/FileFormats/src/main/java/ghidra/file/formats/dump/DumpFileLoader.java
index 12b7c59ca0..b6b4ed3e64 100644
--- a/Ghidra/Features/FileFormats/src/main/java/ghidra/file/formats/dump/DumpFileLoader.java
+++ b/Ghidra/Features/FileFormats/src/main/java/ghidra/file/formats/dump/DumpFileLoader.java
@@ -44,7 +44,8 @@ import ghidra.program.model.symbol.SourceType;
 import ghidra.program.model.symbol.SymbolTable;
 import ghidra.program.model.util.CodeUnitInsertionException;
 import ghidra.util.Msg;
-import ghidra.util.exception.*;
+import ghidra.util.exception.CancelledException;
+import ghidra.util.exception.InvalidInputException;
 import ghidra.util.task.TaskMonitor;
 
 /**
@@ -177,8 +178,7 @@ public class DumpFileLoader extends AbstractProgramWrapperLoader {
 				DumpAddressObject d = daos.get(address);
 				try {
 					MemoryBlockUtils.createInitializedBlock(program, false, d.getRangeName(),
-						address, fileBytes,
-						d.getRVA(), // offset into filebytes
+						address, fileBytes, d.getRVA(), // offset into filebytes
 						d.getLength(), // size
 						d.getComment(), // comment
 						null, // source
@@ -215,7 +215,7 @@ public class DumpFileLoader extends AbstractProgramWrapperLoader {
 						try {
 							m = memory.join(m, next);
 						}
-						catch (MemoryBlockException | LockException | NotFoundException e) {
+						catch (MemoryBlockException | LockException e) {
 							break;
 						}
 						deleted.add(next.getStart());
@@ -281,9 +281,8 @@ public class DumpFileLoader extends AbstractProgramWrapperLoader {
 						symbolTable.createLabel(address, dd.getName(), SourceType.IMPORTED);
 					}
 					catch (InvalidInputException e) {
-						Msg.error(this,
-							"Error creating label " + dd.getName() + " at address " + address +
-								": " + e.getMessage());
+						Msg.error(this, "Error creating label " + dd.getName() + " at address " +
+							address + ": " + e.getMessage());
 					}
 					continue;
 				}
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/LanguageFixupUtil.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/LanguageFixupUtil.java
new file mode 100644
index 0000000000..a6789b116b
--- /dev/null
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/LanguageFixupUtil.java
@@ -0,0 +1,139 @@
+/* ###
+ * IP: GHIDRA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+package ghidra.app.plugin.processors.generic;
+
+import java.util.*;
+
+import ghidra.framework.store.LockException;
+import ghidra.program.database.ProgramDB;
+import ghidra.program.database.symbol.SymbolManager;
+import ghidra.program.model.address.*;
+import ghidra.program.model.lang.AddressLabelInfo;
+import ghidra.program.model.lang.Language;
+import ghidra.program.model.mem.MemoryBlock;
+import ghidra.program.model.mem.MemoryBlockException;
+import ghidra.program.model.symbol.*;
+import ghidra.util.Msg;
+import ghidra.util.exception.*;
+
+/**
+ * {@link LanguageFixupUtil} provides utility method intended for internal language upgrade
+ * situations.
+ */
+public class LanguageFixupUtil {
+
+	/**
+	 * Apply pspec defined memory blocks and default symbols which are considered safe and 
+	 * generally required.  Reconciling symbols is limited to those symbols contained within
+	 * processor defined memory blocks which are not within either the default code or data spaces.
+	 * @param programDB target program
+	 */
+	public static void applyPSpecFixups(ProgramDB programDB) throws CancelledException {
+
+		try {
+
+			Language language = programDB.getLanguage();
+			AddressSpace defaultSpace = language.getDefaultSpace();
+			AddressSpace defaultDataSpace = language.getDefaultDataSpace();
+
+			// Create or fixup processor defined memory blocks
+			// NOTE: Additional translator capability required if block removal is required which 
+			// would likely remove any IMPORTED symbols contained within its bounds
+			AddressSet processorDefinedBlockSet = new AddressSet();
+
+			// Define address set which identifies processor define blocks which are safe to scrub 
+			// of old imported symbols.
+			AddressSet processorDefinedSafeBlockSet = new AddressSet();
+
+			for (MemoryBlockDefinition defaultMemoryBlockDef : language.getDefaultMemoryBlocks()) {
+				try {
+					MemoryBlock block = defaultMemoryBlockDef.fixupBlock(programDB);
+					AddressRange blockRange = block.getAddressRange();
+					processorDefinedBlockSet.add(blockRange);
+					AddressSpace space = block.getStart().getAddressSpace();
+					if (!space.equals(defaultSpace) && !space.equals(defaultDataSpace)) {
+						processorDefinedSafeBlockSet.add(blockRange);
+					}
+				}
+				catch (MemoryBlockException e) {
+					Msg.error(LanguageFixupUtil.class,
+						"Failed to create or fixup processor defined memory block '" +
+							defaultMemoryBlockDef.getBlockName() + "': " + e.getMessage());
+				}
+				catch (LockException e) {
+					throw new RuntimeException(e);  // upgrades require exclusive access
+				}
+			}
+
+			HashSet<Symbol> goodSymbols = new HashSet<>();
+
+			SymbolManager symbolTable = programDB.getSymbolTable();
+			for (AddressLabelInfo labelInfo : language.getDefaultSymbols()) {
+
+				String name = labelInfo.getLabel();
+				Address addr = labelInfo.getAddress();
+
+				// NOTE: For now we only add symbols which are defined within processor-defined blocks
+				if (!processorDefinedBlockSet.contains(addr)) {
+					continue;
+				}
+
+				// Check all symbols within processor-defined blocks
+				Symbol existingSymbol = null;
+				for (Symbol s : symbolTable.getGlobalSymbols(name)) {
+					if (s.getSymbolType() != SymbolType.LABEL) {
+						continue;
+					}
+					if (addr.equals(s.getAddress())) {
+						existingSymbol = s;
+						goodSymbols.add(s);
+					}
+					else if (s.getSource() == SourceType.IMPORTED) {
+						s.delete();
+					}
+				}
+				if (existingSymbol == null) {
+					// Add missing label
+					try {
+						Symbol s = symbolTable.createLabel(addr, name, null, SourceType.IMPORTED);
+						goodSymbols.add(s);
+					}
+					catch (InvalidInputException e) {
+						throw new AssertException(e); // unexpected
+					}
+				}
+			}
+
+			// Remove all symbols with processor defined blocks which are no longer defined.
+			// This is restricted to safe address spaces since loader may have imported other symbols
+			// which we do not want to delete.
+			List<Symbol> deleteSet = new ArrayList<>(); // defered delete to avoid iterator resets
+			for (Symbol s : symbolTable.getSymbols(processorDefinedSafeBlockSet, SymbolType.LABEL,
+				true)) {
+				if (s.getSource() == SourceType.IMPORTED && !goodSymbols.contains(s)) {
+					deleteSet.add(s);
+				}
+			}
+			for (Symbol s : deleteSet) {
+				s.delete();
+			}
+
+		}
+		catch (UnsupportedOperationException e) {
+			// skip
+		}
+	}
+}
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/MemoryBlockDefinition.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/MemoryBlockDefinition.java
index f7de363fb5..13b5ee917e 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/MemoryBlockDefinition.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/generic/MemoryBlockDefinition.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -15,11 +15,15 @@
  */
 package ghidra.app.plugin.processors.generic;
 
+import java.util.List;
+
 import ghidra.framework.store.LockException;
+import ghidra.program.database.ProgramDB;
 import ghidra.program.database.mem.ByteMappingScheme;
 import ghidra.program.model.address.*;
 import ghidra.program.model.listing.Program;
 import ghidra.program.model.mem.*;
+import ghidra.util.Msg;
 import ghidra.util.XmlProgramUtilities;
 import ghidra.util.exception.AssertException;
 import ghidra.util.exception.CancelledException;
@@ -36,18 +40,22 @@ import ghidra.xml.XmlElement;
  */
 public class MemoryBlockDefinition {
 
-	private String blockName;
-	private String addressString;
-	private int length;
-	private boolean initialized;
-	private boolean overlay;
-	private String bitMappedAddress;
-	private String byteMappedAddress;
-	private ByteMappingScheme byteMappingScheme;
-	private boolean readPermission = true;
-	private boolean writePermission = true;
-	private boolean executePermission = false;
-	private boolean isVolatile = false;
+	private final String blockName;
+	private final String addressString;
+	private final int length;
+	private final boolean initialized;
+	private final boolean overlay;
+	private final String bitMappedAddress;
+	private final String byteMappedAddress;
+	private final ByteMappingScheme byteMappingScheme;
+
+	private final String mode;
+	private final boolean readPermission;
+	private final boolean writePermission;
+	private final boolean executePermission;
+	private final boolean isVolatile;
+
+	private static final String DEFAULT_MODE = "rw";
 
 	/**
 	 * Construct <code>MemoryBlockDefinition</code> using a text-based specified.
@@ -62,7 +70,8 @@ public class MemoryBlockDefinition {
 	 * decimations may be specified using a mapping ratio. When specifying a mapping ratio both 
 	 * values must be in the range 1..127 where the right (source-byte count) value must be 
 	 * greater-than-or-equal to the left value (e.g., 2:4).
-	 * @param mode block mode as concatenation of the following mode indicator characters:
+	 * @param mode block mode as concatenation of the following mode indicator characters.  If null
+	 * the default mode (rw) will be used.
 	 * <pre>
 	 *   r - read mode enabled
 	 *   w - write mode enabled
@@ -71,18 +80,33 @@ public class MemoryBlockDefinition {
 	 * </pre>
 	 * @param lengthString length of memory block in bytes (required)
 	 * @param initializedString boolean (y | n | true | false) indicating if memory block is
-	 * initialialized or not (must be null for mapped block specification)
+	 * initialialized or not (ignored for mapped block specification)
 	 * @param overlayString boolean (y | n | true | false) indicating if memory block is an overlay
 	 * (false assumed if null).
 	 * @throws XmlAttributeException if parse failure occurs (NOTE: address parsing is not performed)
 	 */
 	private MemoryBlockDefinition(String blockName, String addressString, String bitMappedAddress,
 			String byteMappedAddressRatio, String mode, String lengthString,
-			String initializedString, String overlayString)
-			throws XmlAttributeException {
+			String initializedString, String overlayString) throws XmlAttributeException {
 
+		this.mode = mode != null ? mode.toLowerCase() : DEFAULT_MODE;
+
+		// Parse specified access mode
+		readPermission = this.mode.indexOf('r') >= 0;
+		writePermission = this.mode.indexOf('w') >= 0;
+		executePermission = this.mode.indexOf('x') >= 0;
+		isVolatile = this.mode.indexOf('v') >= 0;
+
+		if (blockName == null) {
+			throw new XmlAttributeException("Missing default memory block 'name'");
+		}
 		this.blockName = blockName;
+
+		if (addressString == null) {
+			throw new XmlAttributeException("Missing default memory block 'start_address'");
+		}
 		this.addressString = addressString;
+
 		this.bitMappedAddress = bitMappedAddress;
 
 		if (byteMappedAddressRatio != null) {
@@ -98,30 +122,35 @@ public class MemoryBlockDefinition {
 			}
 			else {
 				// 1:1 mapping scheme assumed (null byteMappingScheme)
+				byteMappingScheme = null;
 				byteMappedAddress = byteMappedAddressRatio;
 			}
 		}
-
-		if (mode != null) {
-			mode = mode.toLowerCase();
-			readPermission = mode.indexOf('r') >= 0;
-			writePermission = mode.indexOf('w') >= 0;
-			executePermission = mode.indexOf('x') >= 0;
-			isVolatile = mode.indexOf('v') >= 0;
+		else {
+			byteMappedAddress = null;
+			byteMappingScheme = null;
 		}
+
+		// Parse specified length string
+		int parsedLen = -1;
 		try {
-			length = XmlUtilities.parseInt(lengthString);
+			parsedLen = XmlUtilities.parseInt(lengthString);
 		}
 		catch (NumberFormatException e) {
-			throw new XmlAttributeException(lengthString + " is not a valid integer");
+			// ignore - length will be checked below
 		}
+		if (parsedLen <= 0) {
+			throw new XmlAttributeException(lengthString + " is not a valid 'length'");
+		}
+		length = parsedLen;
+
 		if (initializedString != null) {
 			if (bitMappedAddress != null || byteMappedAddress != null) {
 				throw new XmlAttributeException(
 					"mapped block specifications must not specify initialized attribute");
 			}
-			initialized = XmlUtilities.parseBoolean(initializedString);
 		}
+		initialized = XmlUtilities.parseBoolean(initializedString);
 		overlay = XmlUtilities.parseBoolean(overlayString);
 	}
 
@@ -142,20 +171,164 @@ public class MemoryBlockDefinition {
 		return addr;
 	}
 
+	/**
+	 * {@return memory block name}
+	 */
+	public String getBlockName() {
+		return blockName;
+	}
+
+	/**
+	 * Create or fixup existing block found within specified program.
+	 * @param program target program
+	 * @return new or adjusted memory block
+	 * @throws LockException if program does not have exclusive access
+	 * @throws MemoryBlockException if failed to create or fixup default memory block
+	 */
+	public MemoryBlock fixupBlock(ProgramDB program) throws LockException, MemoryBlockException {
+
+		program.checkExclusiveAccess();
+
+		Memory memory = program.getMemory();
+		MemoryBlock block = memory.getBlock(blockName);
+		if (block == null) {
+			try {
+				Msg.info(this, "Adding process-defined memory block: " + blockName);
+				return createBlock(program);
+			}
+			catch (MemoryConflictException | AddressOverflowException | InvalidAddressException e) {
+				throw new MemoryBlockException("Create block failed", e);
+			}
+		}
+
+		MemoryBlockType blockType = getBlockType();
+		List<MemoryBlockSourceInfo> sourceInfos = block.getSourceInfos();
+
+		if (!blockType.equals(block.getType()) || overlay != block.isOverlay() ||
+			sourceInfos.size() != 1) {
+			throw new MemoryBlockException("Incompatible memory block type");
+		}
+
+		MemoryBlockSourceInfo sourceInfo = sourceInfos.get(0);
+
+		Address addr;
+		Address currentStartAddress;
+		try {
+			addr = parseAddress(addressString, program, "block address");
+
+			currentStartAddress = block.getStart();
+			AddressSpace currentAddressSpace = currentStartAddress.getAddressSpace();
+
+			if (currentAddressSpace instanceof OverlayAddressSpace overlaySpace) {
+				if (overlaySpace.getOverlayedSpace().equals(addr.getAddressSpace())) {
+					throw new MemoryBlockException("Incompatible overlay memory block");
+				}
+				// Redefine overlay block start address for comparison use
+				addr = overlaySpace.getAddressInThisSpaceOnly(addr.getOffset());
+			}
+
+			if (bitMappedAddress != null) {
+				Address mappedAddr = parseAddress(bitMappedAddress, program, "bit-mapped address");
+				if (addr.equals(currentStartAddress) &&
+					mappedAddr.equals(sourceInfo.getMappedRange().get().getMinAddress()) &&
+					length == block.getSize()) {
+					return block;
+				}
+				// We do not currently support modifying default bit-mapped block
+				throw new MemoryBlockException("inconsistent bit-mapped block");
+			}
+			else if (byteMappedAddress != null) {
+				Address mappedAddr =
+					parseAddress(byteMappedAddress, program, "byte-mapped address");
+				if (addr.equals(currentStartAddress) &&
+					mappedAddr.equals(sourceInfo.getMappedRange().get().getMinAddress()) &&
+					length == block.getSize()) {
+					return block;
+				}
+				// We do not currently support modifying default byte-mapped block
+				throw new MemoryBlockException("inconsistent byte-mapped block");
+			}
+		}
+		catch (InvalidAddressException e) {
+			throw new MemoryBlockException("failed to process processor block address", e);
+		}
+
+		if (sourceInfo.getFileBytes().isPresent() || sourceInfo.getMappedRange().isPresent()) {
+			throw new MemoryBlockException("unsupported file or memory-mapped block");
+		}
+
+		if (!addr.equals(currentStartAddress)) {
+			throw new MemoryBlockException(
+				"inconsistent block start address: " + addr + " / " + currentStartAddress);
+		}
+
+		try {
+			if (length > block.getSize()) {
+				// Expand processor defined memory block
+				Msg.info(this, "Expanding processor defined memory block from " + block.getSize() +
+					"-bytes to " + length + "-bytes: " + blockName);
+				MemoryBlock newBlock = memory.createBlock(block, block.getName() + ".exp",
+					block.getEnd().next(), length - block.getSize());
+				MemoryBlock b = memory.join(block, newBlock);
+				if (!b.getName().equals(blockName)) {
+					b.setName(blockName); // preserve block name
+				}
+			}
+			else {
+				Msg.warn(this, "Ignored processor block size reduction: " + blockName);
+			}
+
+			boolean accessAdjusted = false;
+			if (readPermission != block.isRead()) {
+				block.setRead(readPermission);
+				accessAdjusted = true;
+			}
+			if (writePermission != block.isWrite()) {
+				block.setWrite(writePermission);
+				accessAdjusted = true;
+			}
+			if (executePermission != block.isExecute()) {
+				block.setExecute(executePermission);
+				accessAdjusted = true;
+			}
+			if (isVolatile != block.isVolatile()) {
+				block.setVolatile(isVolatile);
+				accessAdjusted = true;
+			}
+			if (accessAdjusted) {
+				Msg.warn(this, "Updated processor block access mode (" + mode + "): " + blockName);
+			}
+
+		}
+		catch (IllegalArgumentException | MemoryConflictException | AddressOverflowException e) {
+			throw new MemoryBlockException("block adjustment failed", e);
+		}
+
+		return block;
+	}
+
+	private MemoryBlockType getBlockType() {
+		if (bitMappedAddress != null) {
+			return MemoryBlockType.BIT_MAPPED;
+		}
+		if (byteMappedAddress != null) {
+			return MemoryBlockType.BYTE_MAPPED;
+		}
+		return MemoryBlockType.DEFAULT;
+	}
+
 	/**
 	 * Create memory block within specified program based upon this block specification.
 	 * @param program target program
+	 * @return newly created memory block
 	 * @throws LockException if program does not have exclusive access required when adding memory blocks.
 	 * @throws MemoryConflictException if this specification conflicts with an existing memory block in program
 	 * @throws AddressOverflowException if memory space constraints are violated by block specification
 	 * @throws InvalidAddressException if address defined by this block specification is invalid
 	 * for the specified program.  May also indicate an improperly formatted address attribute.
 	 */
-	public void createBlock(Program program) throws LockException, MemoryConflictException,
+	public MemoryBlock createBlock(Program program) throws LockException, MemoryConflictException,
 			AddressOverflowException, InvalidAddressException {
-		if (blockName == null || addressString == null || length <= 0) {
-			return;
-		}
 
 		Memory mem = program.getMemory();
 		Address addr = parseAddress(addressString, program, "block address");
@@ -172,9 +345,8 @@ public class MemoryBlockDefinition {
 		}
 		else if (initialized) {
 			try {
-				block =
-					mem.createInitializedBlock(blockName, addr, length, (byte) 0,
-						TaskMonitor.DUMMY, overlay);
+				block = mem.createInitializedBlock(blockName, addr, length, (byte) 0,
+					TaskMonitor.DUMMY, overlay);
 			}
 			catch (CancelledException e) {
 				throw new AssertException(e); // unexpected
@@ -187,6 +359,7 @@ public class MemoryBlockDefinition {
 		block.setWrite(writePermission);
 		block.setExecute(executePermission);
 		block.setVolatile(isVolatile);
+		return block;
 	}
 
 	@Override
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java
index 330b0a80ef..e98c7f6cea 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java
@@ -47,6 +47,7 @@ import ghidra.program.model.util.ProcessorSymbolType;
 import ghidra.sleigh.grammar.SleighPreprocessor;
 import ghidra.sleigh.grammar.SourceFileIndexer;
 import ghidra.util.*;
+import ghidra.util.exception.InvalidInputException;
 import ghidra.util.task.TaskMonitor;
 import ghidra.util.xml.SpecXmlUtils;
 import ghidra.xml.*;
@@ -787,10 +788,9 @@ public class SleighLanguage implements Language {
 						AddressLabelInfo info;
 						try {
 							info = new AddressLabelInfo(startAddress, rangeSize, labelName, comment,
-								false,
-								isEntry, type, isVolatile);
+								false, isEntry, type, isVolatile);
 						}
-						catch (AddressOverflowException e) {
+						catch (AddressOverflowException | InvalidInputException e) {
 							throw new XmlParseException("invalid symbol definition: " + labelName,
 								e);
 						}
@@ -1242,9 +1242,7 @@ public class SleighLanguage implements Language {
 		ManualEntry manualEntry = null;
 		int maxInCommon = -1;
 
-		Iterator<Entry<String, ManualEntry>> ii = subMap.entrySet().iterator();
-		while (ii.hasNext()) {
-			Entry<String, ManualEntry> mapEntry = ii.next();
+		for (Entry<String, ManualEntry> mapEntry : subMap.entrySet()) {
 			String key = mapEntry.getKey();
 			if (instruction.startsWith(key) && key.length() > maxInCommon) {
 				manualEntry = mapEntry.getValue();
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/ProgramDB.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/ProgramDB.java
index 31b9a991de..1b641080bb 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/ProgramDB.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/ProgramDB.java
@@ -22,6 +22,7 @@ import java.util.*;
 import org.apache.commons.lang3.StringUtils;
 
 import db.DBHandle;
+import ghidra.app.plugin.processors.generic.LanguageFixupUtil;
 import ghidra.app.plugin.processors.sleigh.SleighLanguage;
 import ghidra.framework.Application;
 import ghidra.framework.data.DomainObjectAdapterDB;
@@ -2065,8 +2066,10 @@ public class ProgramDB extends DomainObjectAdapterDB implements Program, ChangeM
 						newCompilerSpecID = translator.getNewCompilerSpecID(compilerSpecID);
 					}
 					Msg.info(this, "Setting language for Program " + getName() + ": " + translator);
-					Msg.info(this, "Setting compiler spec for Program " + getName() + ": " +
-						compilerSpecID + " -> " + newCompilerSpecID);
+					if (!compilerSpecID.equals(newCompilerSpecID)) {
+						Msg.info(this, "Setting compiler spec for Program " + getName() + ": " +
+							compilerSpecID + " -> " + newCompilerSpecID);
+					}
 				}
 				else if (!forceRedisassembly && language.getVersion() == languageVersion &&
 					language.getMinorVersion() == languageMinorVersion) {
@@ -2138,6 +2141,9 @@ public class ProgramDB extends DomainObjectAdapterDB implements Program, ChangeM
 					translator.fixupInstructions(this, translator.getOldLanguage(), monitor);
 				}
 
+				// apply pspec default markup as defined by translator and pspec
+				LanguageFixupUtil.applyPSpecFixups(this);
+
 				dataMap.put(LANGUAGE_ID, languageID.getIdAsString());
 				dataMap.put(COMPILER_SPEC_ID, compilerSpecID.getIdAsString());
 				dataMap.put(LANGUAGE_VERSION, languageVersion + "." + languageMinorVersion);
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/mem/MemoryMapDB.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/mem/MemoryMapDB.java
index 6c262f3512..6d609c8eb1 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/mem/MemoryMapDB.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/database/mem/MemoryMapDB.java
@@ -941,7 +941,7 @@ public class MemoryMapDB implements Memory, ManagerDB {
 	@Override
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
 			throws MemoryBlockException, MemoryConflictException, AddressOverflowException,
-			NotFoundException, LockException {
+			LockException {
 		lock.acquire();
 		try {
 			program.checkExclusiveAccess();
@@ -986,8 +986,7 @@ public class MemoryMapDB implements Memory, ManagerDB {
 	}
 
 	@Override
-	public void split(MemoryBlock block, Address addr)
-			throws MemoryBlockException, NotFoundException, LockException {
+	public void split(MemoryBlock block, Address addr) throws MemoryBlockException, LockException {
 		lock.acquire();
 		try {
 			program.checkExclusiveAccess();
@@ -1037,7 +1036,7 @@ public class MemoryMapDB implements Memory, ManagerDB {
 
 	@Override
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		lock.acquire();
 		try {
 			// swap if second block is before first block
@@ -1111,7 +1110,7 @@ public class MemoryMapDB implements Memory, ManagerDB {
 
 	@Override
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		lock.acquire();
 		try {
 			checkBlock(uninitializedBlock);
@@ -1149,7 +1148,7 @@ public class MemoryMapDB implements Memory, ManagerDB {
 
 	@Override
 	public MemoryBlock convertToUninitialized(MemoryBlock initializedBlock)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		lock.acquire();
 		try {
 			program.checkExclusiveAccess();
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/data/ProgramArchitectureTranslator.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/data/ProgramArchitectureTranslator.java
index 67a42c6043..3bc1159702 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/data/ProgramArchitectureTranslator.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/data/ProgramArchitectureTranslator.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -15,10 +15,12 @@
  */
 package ghidra.program.model.data;
 
+import ghidra.program.database.ProgramDB;
 import ghidra.program.model.lang.*;
 import ghidra.program.model.listing.IncompatibleLanguageException;
 import ghidra.program.util.DefaultLanguageService;
 import ghidra.program.util.LanguageTranslatorAdapter;
+import ghidra.util.task.TaskMonitor;
 
 public class ProgramArchitectureTranslator extends LanguageTranslatorAdapter {
 
@@ -40,9 +42,8 @@ public class ProgramArchitectureTranslator extends LanguageTranslatorAdapter {
 
 	public ProgramArchitectureTranslator(LanguageID oldLanguageId, int oldLanguageVersion,
 			CompilerSpecID oldCompilerSpecId, Language newLanguage,
-			CompilerSpecID newCompilerSpecId)
-			throws LanguageNotFoundException, CompilerSpecNotFoundException,
-			IncompatibleLanguageException {
+			CompilerSpecID newCompilerSpecId) throws LanguageNotFoundException,
+			CompilerSpecNotFoundException, IncompatibleLanguageException {
 		this(getLanguage(oldLanguageId, oldLanguageVersion), oldCompilerSpecId, newLanguage,
 			newCompilerSpecId);
 	}
@@ -65,5 +66,4 @@ public class ProgramArchitectureTranslator extends LanguageTranslatorAdapter {
 		return newCompilerSpec;
 	}
 
-
 }
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/AddressLabelInfo.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/AddressLabelInfo.java
index ef114b9018..566fddce68 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/AddressLabelInfo.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/AddressLabelInfo.java
@@ -17,7 +17,9 @@ package ghidra.program.model.lang;
 
 import ghidra.program.model.address.Address;
 import ghidra.program.model.address.AddressOverflowException;
+import ghidra.program.model.symbol.SymbolUtilities;
 import ghidra.program.model.util.ProcessorSymbolType;
+import ghidra.util.exception.InvalidInputException;
 
 /**
  * <CODE>AddressLabelInfo</CODE> is a utility class for storing
@@ -35,7 +37,7 @@ public class AddressLabelInfo implements Comparable<AddressLabelInfo> {
 	private ProcessorSymbolType processorSymbolType;
 	private int sizeInBytes;
 	private Boolean isVolatile;
-	
+
 	/**
 	 * Constructor for class AddressLabelInfo
 	 * 
@@ -47,17 +49,22 @@ public class AddressLabelInfo implements Comparable<AddressLabelInfo> {
 	 * @param	isEntry			boolean describes if this object is an entry label for the Address 'addr'
 	 * @param	type			ProcessorSymbolType the type of symbol
 	 * @param	isVolatile		Boolean describes if the memory at this address is volatile
+	 * @throws AddressOverflowException if sizeInBytes cause an overflow relative to address
+	 * @throws InvalidInputException if an invalid label name is specified
 	 */
-	public AddressLabelInfo(Address addr, Integer sizeInBytes, String label, String description, boolean isPrimary, 
-			boolean isEntry, ProcessorSymbolType type, Boolean isVolatile) throws AddressOverflowException {
+	public AddressLabelInfo(Address addr, Integer sizeInBytes, String label, String description,
+			boolean isPrimary, boolean isEntry, ProcessorSymbolType type, Boolean isVolatile)
+			throws AddressOverflowException, InvalidInputException {
+		SymbolUtilities.validateName(label);
 		this.addr = addr;
-		if ( sizeInBytes == null || sizeInBytes <= 0 ) {
+		if (sizeInBytes == null || sizeInBytes <= 0) {
 			// Default size in addressable units
 			this.sizeInBytes = addr.getAddressSpace().getAddressableUnitSize();
-		} else {
+		}
+		else {
 			this.sizeInBytes = sizeInBytes;
 		}
-		this.endAddr = this.addr.addNoWrap(this.sizeInBytes-1);
+		this.endAddr = this.addr.addNoWrap(this.sizeInBytes - 1);
 		this.label = label;
 		this.description = description;
 		this.isPrimary = isPrimary;
@@ -72,21 +79,21 @@ public class AddressLabelInfo implements Comparable<AddressLabelInfo> {
 	public final Address getAddress() {
 		return addr;
 	}
-	
+
 	/**
 	 * @return the object's end address.
 	 */
 	public final Address getEndAddress() {
 		return endAddr;
 	}
-	
+
 	/**
 	 * @return the object's label or alias.
 	 */
 	public final String getLabel() {
 		return label;
 	}
-	
+
 	/**
 	 * @return the object's description if it has one, null otherwise
 	 */
@@ -101,14 +108,14 @@ public class AddressLabelInfo implements Comparable<AddressLabelInfo> {
 	public final int getByteSize() {
 		return sizeInBytes;
 	}
-	
+
 	/**
 	 * @return whether the object is the primary label at the address.
 	 */
 	public final boolean isPrimary() {
 		return isPrimary;
 	}
-	
+
 	/**
 	 * @return whether the object is volatile.
 	 * Boolean.False when the address is explicitly not volatile.
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/Memory.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/Memory.java
index 3b756fc30a..4fe26964ff 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/Memory.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/Memory.java
@@ -25,7 +25,6 @@ import ghidra.program.model.address.*;
 import ghidra.program.model.listing.Program;
 import ghidra.program.model.symbol.OffsetReference;
 import ghidra.util.exception.CancelledException;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 /**
@@ -462,16 +461,14 @@ public interface Memory extends AddressSetView {
 	 * @param newStartAddr new start address for block
 	 * @param monitor task monitor so the move block can be canceled
 	 * @throws LockException if exclusive lock not in place (see haveLock())
+	 * @throws MemoryBlockException if block movement is not permitted
 	 * @throws MemoryConflictException if move would cause
 	 * blocks to overlap.
-	 * @throws MemoryBlockException if block movement is not permitted
 	 * @throws AddressOverflowException if block movement would violate bounds of address space
-	 * @throws NotFoundException if memoryBlock does not exist in
-	 *   this memory.
 	 */
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
 			throws LockException, MemoryBlockException, MemoryConflictException,
-			AddressOverflowException, NotFoundException;
+			AddressOverflowException;
 
 	/**
 	 * Split a block at the given addr and create a new block
@@ -479,14 +476,11 @@ public interface Memory extends AddressSetView {
 	 * @param block block to be split into two
 	 * @param addr address (within block) that will be the
 	 * start of new block
-	 * @throws LockException if exclusive lock not in place (see haveLock())
-	 * @throws NotFoundException thrown if block does not exist
-	 * in memory
 	 * @throws MemoryBlockException memory split not permitted
+	 * @throws LockException if exclusive lock not in place (see haveLock())
 	 * @throws AddressOutOfBoundsException thrown if address is not in the block
 	 */
-	public void split(MemoryBlock block, Address addr)
-			throws MemoryBlockException, LockException, NotFoundException;
+	public void split(MemoryBlock block, Address addr) throws MemoryBlockException, LockException;
 
 	/**
 	 * Join the two blocks to create a single memory block.
@@ -499,7 +493,7 @@ public interface Memory extends AddressSetView {
 	 * not contiguous in the address space,
 	 */
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws LockException, MemoryBlockException, NotFoundException;
+			throws LockException, MemoryBlockException;
 
 	/**
 	 * Convert an existing uninitialized block with an initialized block.
@@ -512,10 +506,20 @@ public interface Memory extends AddressSetView {
 	 * the same.
 	 */
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws LockException, MemoryBlockException, NotFoundException;
+			throws LockException, MemoryBlockException;
 
-	public MemoryBlock convertToUninitialized(MemoryBlock itializedBlock)
-			throws MemoryBlockException, NotFoundException, LockException;
+	/**
+	 * Convert an existing initialized block with an uninitialized block.
+	 * Block will discard any associated memory bytes and drop source info.
+	 * @param initializedBlock uninitialized block to convert
+	 * @return the converted block
+	 * @throws LockException if exclusive lock not in place (see haveLock())
+	 * @throws MemoryBlockException if there is no block in memory
+	 * at the same address as block or if the block lengths are not
+	 * the same.
+	 */
+	public MemoryBlock convertToUninitialized(MemoryBlock initializedBlock)
+			throws MemoryBlockException, LockException;
 
 	/**
 	  * Finds a sequence of contiguous bytes that match the
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/MemoryBlockException.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/MemoryBlockException.java
index a0464dd1c8..92cb2cbfad 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/MemoryBlockException.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/MemoryBlockException.java
@@ -1,13 +1,12 @@
 /* ###
  * IP: GHIDRA
- * REVIEWED: YES
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -16,7 +15,6 @@
  */
 package ghidra.program.model.mem;
 
-
 /**
  * Exception thrown for memory block-related problems.
  */
@@ -29,11 +27,21 @@ public class MemoryBlockException extends MemoryAccessException {
 	public MemoryBlockException() {
 		super();
 	}
+
 	/**
 	 * Constructs a new MemoryBlockException with a detailed message.
 	 * @param msg detailed message
 	 */
-    public MemoryBlockException(String msg) {
-        super(msg);
-    }
-} 
+	public MemoryBlockException(String msg) {
+		super(msg);
+	}
+
+	/**
+	 * Constructs a new MemoryBlockException with a detailed message.
+	 * @param msg detailed message
+	 * @param cause original cause of this exception
+	 */
+	public MemoryBlockException(String msg, Throwable cause) {
+		super(msg, cause);
+	}
+}
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/StubMemory.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/StubMemory.java
index ae14cf4aa0..aad0ffc499 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/StubMemory.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/mem/StubMemory.java
@@ -24,7 +24,6 @@ import ghidra.framework.store.LockException;
 import ghidra.program.database.mem.*;
 import ghidra.program.model.address.*;
 import ghidra.program.model.listing.Program;
-import ghidra.util.exception.NotFoundException;
 import ghidra.util.task.TaskMonitor;
 
 /**
@@ -241,31 +240,31 @@ public class StubMemory extends AddressSet implements Memory {
 	@Override
 	public void moveBlock(MemoryBlock block, Address newStartAddr, TaskMonitor monitor)
 			throws LockException, MemoryBlockException, MemoryConflictException,
-			AddressOverflowException, NotFoundException {
+			AddressOverflowException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public void split(MemoryBlock block, Address addr)
-			throws MemoryBlockException, LockException, NotFoundException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock join(MemoryBlock blockOne, MemoryBlock blockTwo)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToInitialized(MemoryBlock uninitializedBlock, byte initialValue)
-			throws LockException, MemoryBlockException, NotFoundException {
+			throws LockException, MemoryBlockException {
 		throw new UnsupportedOperationException();
 	}
 
 	@Override
 	public MemoryBlock convertToUninitialized(MemoryBlock initializedBlock)
-			throws MemoryBlockException, NotFoundException, LockException {
+			throws MemoryBlockException, LockException {
 		throw new UnsupportedOperationException();
 	}
 
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslator.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslator.java
index 3366310206..2622304812 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslator.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslator.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -15,6 +15,7 @@
  */
 package ghidra.program.util;
 
+import ghidra.program.database.ProgramDB;
 import ghidra.program.model.address.Address;
 import ghidra.program.model.address.AddressSpace;
 import ghidra.program.model.lang.*;
@@ -34,7 +35,7 @@ import ghidra.util.task.TaskMonitor;
  * instantiate Language, AddressSpace, AddressFactory or Register objects until isValid() is invoked.
  */
 public interface LanguageTranslator extends ExtensionPoint {
-	
+
 	/**
 	 * Validate translator to complete initialization and ensure language compatibility.
 	 * This method will be invoked by the LanguageTranslatorFactory before handing out this
@@ -42,7 +43,7 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 * @return true if translator successfully validated
 	 */
 	public boolean isValid();
-	
+
 	/**
 	 * Returns old language
 	 * @throws IllegalStateException if instance has not been validated
@@ -54,27 +55,27 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 * Returns new language
 	 */
 	public Language getNewLanguage();
-	
+
 	/**
 	 * Returns old language name
 	 */
 	public LanguageID getOldLanguageID();
-	
+
 	/**
 	 * Returns new language name
 	 */
 	public LanguageID getNewLanguageID();
-	
+
 	/**
 	 * Returns old language version
 	 */
 	public int getOldVersion();
-	
+
 	/**
 	 * Returns new language version
 	 */
 	public int getNewVersion();
-	
+
 	/**
 	 * Translate BASE address spaces (Overlay spaces are not handled)
 	 * @param oldSpaceName old space name
@@ -92,7 +93,7 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 * @see #getOldRegisterContaining(Address) 
 	 */
 	public Register getOldRegister(Address oldAddr, int size);
-	
+
 	/**
 	 * Get the largest old register which contains the specified oldAddr
 	 * @param oldAddr old register address which may be offcut
@@ -104,14 +105,14 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 * Returns the old processor context register or null if not defined
 	 */
 	public Register getOldContextRegister();
-	
+
 	/**
 	 * Find new register which corresponds to the specified old register.
 	 * @param oldReg old register
 	 * @return new register or null if corresponding register not found.
 	 */
 	public Register getNewRegister(Register oldReg);
-	
+
 	/**
 	 * Returns the new processor context register or null if not defined
 	 */
@@ -150,7 +151,8 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 * @throws CompilerSpecNotFoundException if new compiler spec not found based upon 
 	 * translator mappings.
 	 */
-	public CompilerSpec getOldCompilerSpec(CompilerSpecID oldCompilerSpecID) throws CompilerSpecNotFoundException;
+	public CompilerSpec getOldCompilerSpec(CompilerSpecID oldCompilerSpecID)
+			throws CompilerSpecNotFoundException;
 
 	/**
 	 * Invoked after Program language upgrade has completed.  
@@ -172,4 +174,5 @@ public interface LanguageTranslator extends ExtensionPoint {
 	 */
 	public void fixupInstructions(Program program, Language oldLanguage, TaskMonitor monitor)
 			throws Exception, CancelledException;
+
 }
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorAdapter.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorAdapter.java
index 2e03b03a56..4eb2168573 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorAdapter.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorAdapter.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -225,9 +225,7 @@ public abstract class LanguageTranslatorAdapter implements LanguageTranslator {
 	protected static AddressSpace findSpaceSameName(AddressSpace oldSpace,
 			ArrayList<AddressSpace> newSpaces) throws IncompatibleLanguageException {
 
-		Iterator<AddressSpace> it = newSpaces.iterator();
-		while (it.hasNext()) {
-			AddressSpace space = it.next();
+		for (AddressSpace space : newSpaces) {
 			if (space.getName().equals(oldSpace.getName())) {
 				if (oldSpace.getSize() > space.getSize()) {
 					throw new IncompatibleLanguageException("Old language space (" +
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorFactory.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorFactory.java
index e1d1ab97ff..cbc464a876 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorFactory.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/LanguageTranslatorFactory.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -20,6 +20,7 @@ import java.util.*;
 
 import generic.jar.ResourceFile;
 import ghidra.framework.Application;
+import ghidra.program.database.ProgramDB;
 import ghidra.program.model.address.Address;
 import ghidra.program.model.address.AddressSpace;
 import ghidra.program.model.lang.*;
@@ -405,10 +406,10 @@ public class LanguageTranslatorFactory {
 	}
 
 	/**
-	 * 
+	 * Get language translator
 	 * @param versionTranslatorList sorted list of version translators
-	 * @param version
-	 * @return
+	 * @param version old/from language version 
+	 * @return translator from specified version or next greater versionor null if not found
 	 */
 	private LanguageTranslator getNextTranslator(List<LanguageTranslator> versionTranslatorList,
 			int version) {
@@ -561,4 +562,5 @@ class FactoryLanguageTranslator implements LanguageTranslator {
 	public String toString() {
 		return t1.toString() + "; " + System.getProperty("line.separator") + t2.toString();
 	}
+
 }
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/OldLanguage.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/OldLanguage.java
index 1d2459058e..21b55e2ab0 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/OldLanguage.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/OldLanguage.java
@@ -289,7 +289,8 @@ class OldLanguage implements Language {
 			throw new SAXException("Missing required 'spaces' element");
 		}
 		if (!registersFound) {
-			throw new SAXException("Missing required 'registers' element");
+			// register mapping will not be performed
+			registerMgr = (new RegisterBuilder()).getRegisterManager();
 		}
 	}
 
diff --git a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/SimpleLanguageTranslator.java b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/SimpleLanguageTranslator.java
index f0f64cad69..e7d462b263 100644
--- a/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/SimpleLanguageTranslator.java
+++ b/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/SimpleLanguageTranslator.java
@@ -4,9 +4,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
- * 
+ *
  *      http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -471,9 +471,4 @@ class SimpleLanguageTranslator extends LanguageTranslatorAdapter {
 		contextSettings.put(name, val);
 	}
 
-	public CompilerSpec getCompilerSpec() {
-		// TODO Auto-generated method stub
-		return null;
-	}
-
 }
diff --git a/Ghidra/Processors/RISCV/certification.manifest b/Ghidra/Processors/RISCV/certification.manifest
index 53b21f900f..86ac4c8328 100644
--- a/Ghidra/Processors/RISCV/certification.manifest
+++ b/Ghidra/Processors/RISCV/certification.manifest
@@ -1,15 +1,12 @@
 ##VERSION: 2.0
 Module.manifest||GHIDRA||||END|
 README.md||GHIDRA||||END|
-data/languages/RV32G.pspec||GHIDRA||||END|
-data/languages/RV32GC.pspec||GHIDRA||||END|
-data/languages/RV32I.pspec||GHIDRA||||END|
-data/languages/RV32IC.pspec||GHIDRA||||END|
-data/languages/RV32IMC.pspec||GHIDRA||||END|
-data/languages/RV64G.pspec||GHIDRA||||END|
-data/languages/RV64GC.pspec||GHIDRA||||END|
-data/languages/RV64I.pspec||GHIDRA||||END|
-data/languages/RV64IC.pspec||GHIDRA||||END|
+data/languages/RV32.pspec||GHIDRA||||END|
+data/languages/RV64.pspec||GHIDRA||||END|
+data/languages/andestar_v5.instr.sinc||GHIDRA||||END|
+data/languages/andestar_v5.ldefs||GHIDRA||||END|
+data/languages/andestar_v5.slaspec||GHIDRA||||END|
+data/languages/old/riscv_deprecated.ldefs||GHIDRA||||END|
 data/languages/riscv.csr.sinc||GHIDRA||||END|
 data/languages/riscv.custom.sinc||GHIDRA||||END|
 data/languages/riscv.ilp32d.slaspec||GHIDRA||||END|
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32.pspec b/Ghidra/Processors/RISCV/data/languages/RV32.pspec
new file mode 100644
index 0000000000..8ad55ead2f
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/RV32.pspec
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+  <programcounter register="pc"/>
+  <context_data>
+    <context_set space="ram">
+      <set name="MXL" val="1"/>
+    </context_set>
+  </context_data>
+  
+  <default_memory_blocks>
+    <memory_block name="csr" start_address="csreg:0x0" length="0x4000" initialized="false"/>
+  </default_memory_blocks>
+  
+  <!-- TODO: add include directive and move to shared include -->
+  <default_symbols>
+     <symbol name="ustatus"       address="csreg:0x000"       size="4" description="" />
+     <symbol name="fflags"        address="csreg:0x001"       size="4" description="" />
+     <symbol name="frm"           address="csreg:0x002"       size="4" description="" />
+     <symbol name="fcsr"          address="csreg:0x003"       size="4" description="" />
+     <symbol name="uie"           address="csreg:0x004"       size="4" description="" />
+     <symbol name="utvec"         address="csreg:0x005"       size="4" description="" />
+
+     <symbol name="vstart"        address="csreg:0x008"       size="4" description="" />
+     <symbol name="vxsat"         address="csreg:0x009"       size="4" description="" />
+     <symbol name="vxrm"          address="csreg:0x00a"       size="4" description="" />
+     <symbol name="vcsr"          address="csreg:0x00f"       size="4" description="" />
+
+
+     <symbol name="uscratch"      address="csreg:0x040"       size="4" description="" />
+     <symbol name="uepc"                 address="next"       size="4" description="" />
+     <symbol name="ucause"               address="next"       size="4" description="" />
+     <symbol name="utval"                address="next"       size="4" description="" />
+     <symbol name="uip"                  address="next"       size="4" description="" />
+
+
+     <symbol name="sstatus"       address="csreg:0x100"       size="4" description="" />
+     <symbol name="sedeleg"              address="next"       size="4" description="" />
+     <symbol name="sideleg"              address="next"       size="4" description="" />
+     <symbol name="sie"                  address="next"       size="4" description="" />
+     <symbol name="stvec"                address="next"       size="4" description="" />
+     <symbol name="scounteren"           address="next"       size="4" description="" />
+     
+
+     <symbol name="sscratch"      address="csreg:0x140"       size="4" description="" />
+     <symbol name="sepc"                 address="next"       size="4" description="" />
+     <symbol name="scause"               address="next"       size="4" description="" />
+     <symbol name="stval"                address="next"       size="4" description="" />
+     <symbol name="sip"                  address="next"       size="4" description="" />
+
+
+     <symbol name="satp"          address="csreg:0x180"       size="4" description="" />
+
+
+     <symbol name="vsstatus"      address="csreg:0x200"       size="4" description="" />
+     <symbol name="vsie"          address="csreg:0x204"       size="4" description="" />
+     <symbol name="vstvec"               address="next"       size="4" description="" />
+
+
+     <symbol name="vsscratch"     address="csreg:0x240"       size="4" description="" />
+     <symbol name="vsepc"                address="next"       size="4" description="" />
+     <symbol name="vscause"              address="next"       size="4" description="" />
+     <symbol name="vstval"               address="next"       size="4" description="" />
+     <symbol name="vsip"                 address="next"       size="4" description="" />
+
+
+     <symbol name="vsatp"         address="csreg:0x280"       size="4" description="" />
+
+
+     <symbol name="mstatus"       address="csreg:0x300"       size="4" description="" />
+     <symbol name="misa"                 address="next"       size="4" description="" />
+     <symbol name="medeleg"              address="next"       size="4" description="" />
+     <symbol name="mideleg"              address="next"       size="4" description="" />
+     <symbol name="mie"                  address="next"       size="4" description="" />
+     <symbol name="mtvec"                address="next"       size="4" description="" />
+     <symbol name="mcounteren"           address="next"       size="4" description="" />
+
+
+     <symbol name="mstatush"      address="csreg:0x310"       size="4" description="" />
+
+
+     <symbol name="mcountinhibit" address="csreg:0x320"       size="4" description="" />
+     <symbol name="mhpmevent3"    address="csreg:0x323"       size="4" description="" />
+     <symbol name="mhpmevent4"    address="csreg:0x324"       size="4" description="" />
+     <symbol name="mhpmevent5"    address="csreg:0x325"       size="4" description="" />
+     <symbol name="mhpmevent6"    address="csreg:0x326"       size="4" description="" />
+     <symbol name="mhpmevent7"    address="csreg:0x327"       size="4" description="" />
+
+     <symbol name="mhpmevent8"    address="csreg:0x328"       size="4" description="" />
+     <symbol name="mhpmevent9"    address="csreg:0x329"       size="4" description="" />
+     <symbol name="mhpmevent10"   address="csreg:0x32a"       size="4" description="" />
+     <symbol name="mhpmevent11"   address="csreg:0x32b"       size="4" description="" />
+     <symbol name="mhpmevent12"   address="csreg:0x32c"       size="4" description="" />
+     <symbol name="mhpmevent13"   address="csreg:0x32d"       size="4" description="" />
+     <symbol name="mhpmevent14"   address="csreg:0x32e"       size="4" description="" />
+     <symbol name="mhpmevent15"   address="csreg:0x32f"       size="4" description="" />
+
+     <symbol name="mhpmevent16"   address="csreg:0x330"       size="4" description="" />
+     <symbol name="mhpmevent17"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent18"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent19"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent20"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent21"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent22"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent23"          address="next"       size="4" description="" />
+
+     <symbol name="mhpmevent24"   address="csreg:0x338"       size="4" description="" />
+     <symbol name="mhpmevent25"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent26"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent27"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent28"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent29"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent30"          address="next"       size="4" description="" />
+     <symbol name="mhpmevent31"          address="next"       size="4" description="" />
+
+     <symbol name="mscratch"      address="csreg:0x340"       size="4" description="" />
+     <symbol name="mepc"          address="csreg:0x341"       size="4" description="" />
+     <symbol name="mcause"        address="csreg:0x342"       size="4" description="" />
+     <symbol name="mtval"         address="csreg:0x343"       size="4" description="" />
+     <symbol name="mip"           address="csreg:0x344"       size="4" description="" />
+
+     <symbol name="mtinst"        address="csreg:0x34a"       size="4" description="" />
+     <symbol name="mtval2"        address="csreg:0x34b"       size="4" description="" />
+
+
+     <symbol name="mbase"         address="csreg:0x380"       size="4" description="" />
+     <symbol name="mbound"        address="csreg:0x381"       size="4" description="" />
+     <symbol name="mibase"        address="csreg:0x382"       size="4" description="" />
+     <symbol name="mibound"       address="csreg:0x383"       size="4" description="" />
+     <symbol name="mdbase"        address="csreg:0x384"       size="4" description="" />
+     <symbol name="mdbound"       address="csreg:0x385"       size="4" description="" />
+
+
+     <symbol name="pmpcfg0"       address="csreg:0x3a0"       size="4" description="" />
+     <symbol name="pmpcfg1"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg2"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg3"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg4"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg5"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg6"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg7"              address="next"       size="4" description="" />
+
+     <symbol name="pmpcfg8"       address="csreg:0x3a8"       size="4" description="" />
+     <symbol name="pmpcfg9"              address="next"       size="4" description="" />
+     <symbol name="pmpcfg10"             address="next"       size="4" description="" />
+     <symbol name="pmpcfg11"             address="next"       size="4" description="" />
+     <symbol name="pmpcfg12"             address="next"       size="4" description="" />
+     <symbol name="pmpcfg13"             address="next"       size="4" description="" />
+     <symbol name="pmpcfg14"             address="next"       size="4" description="" />
+     <symbol name="pmpcfg15"             address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr0"      address="csreg:0x3b0"       size="4" description="" />
+     <symbol name="pmpaddr1"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr2"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr3"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr4"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr5"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr6"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr7"             address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr8"      address="csreg:0x3b8"       size="4" description="" />
+     <symbol name="pmpaddr9"             address="next"       size="4" description="" />
+     <symbol name="pmpaddr10"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr11"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr12"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr13"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr14"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr15"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr16"     address="csreg:0x3c0"       size="4" description="" />
+     <symbol name="pmpaddr17"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr18"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr19"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr20"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr21"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr22"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr23"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr24"     address="csreg:0x3c8"       size="4" description="" />
+     <symbol name="pmpaddr25"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr26"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr27"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr28"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr29"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr30"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr31"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr32"     address="csreg:0x3d0"       size="4" description="" />
+     <symbol name="pmpaddr33"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr34"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr35"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr36"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr37"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr38"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr39"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr40"     address="csreg:0x3d8"       size="4" description="" />
+     <symbol name="pmpaddr41"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr42"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr43"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr44"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr45"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr46"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr47"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr48"     address="csreg:0x3e0"       size="4" description="" />
+     <symbol name="pmpaddr49"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr50"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr51"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr52"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr53"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr54"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr55"            address="next"       size="4" description="" />
+
+     <symbol name="pmpaddr56"     address="csreg:0x3e8"       size="4" description="" />
+     <symbol name="pmpaddr57"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr58"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr59"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr60"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr61"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr62"            address="next"       size="4" description="" />
+     <symbol name="pmpaddr63"            address="next"       size="4" description="" />
+
+
+     <symbol name="scontext"      address="csreg:0x5a8"       size="4" description="" />
+
+
+     <symbol name="hstatus"       address="csreg:0x600"       size="4" description="" />
+     <symbol name="hedeleg"       address="csreg:0x602"       size="4" description="" />
+     <symbol name="hideleg"       address="csreg:0x603"       size="4" description="" />
+     <symbol name="hie"           address="csreg:0x604"       size="4" description="" />
+     <symbol name="htimedelta"    address="csreg:0x605"       size="4" description="" />
+     <symbol name="hcounteren"    address="csreg:0x606"       size="4" description="" />
+     <symbol name="hgeie"         address="csreg:0x607"       size="4" description="" />
+
+
+     <symbol name="htimedeltah"   address="csreg:0x615"       size="4" description="" />
+
+
+     <symbol name="htval"         address="csreg:0x643"       size="4" description="" />
+     <symbol name="hip"           address="csreg:0x644"       size="4" description="" />
+     <symbol name="hvip"          address="csreg:0x645"       size="4" description="" />
+
+     <symbol name="htinst"        address="csreg:0x64a"       size="4" description="" />
+
+
+     <symbol name="hgatp"         address="csreg:0x680"       size="4" description="" />
+
+
+     <symbol name="hcontext"      address="csreg:0x6a8"       size="4" description="" />
+
+
+     <symbol name="tselect"       address="csreg:0x7a0"       size="4" description="" />
+     <symbol name="tdata1"        address="csreg:0x7a1"       size="4" description="" />
+     <symbol name="tdata2"        address="csreg:0x7a2"       size="4" description="" />
+     <symbol name="tdata3"        address="csreg:0x7a3"       size="4" description="" />
+
+     <symbol name="mcontext"      address="csreg:0x7a8"       size="4" description="" />
+
+     <symbol name="dcsr"          address="csreg:0x7b0"       size="4" description="" />
+     <symbol name="dpc"           address="csreg:0x7b1"       size="4" description="" />
+     <symbol name="dscratch0"     address="csreg:0x7b2"       size="4" description="" />
+     <symbol name="dscratch1"     address="csreg:0x7b3"       size="4" description="" />
+
+
+     <symbol name="mcycle"        address="csreg:0xa00"       size="4" description="" />
+     <symbol name="minstret"      address="csreg:0xa02"       size="4" description="" />
+     <symbol name="mhpmcounter3"  address="csreg:0xa03"       size="4" description="" />
+     <symbol name="mhpmcounter4"         address="next"       size="4" description="" />
+     <symbol name="mhpmcounter5"         address="next"       size="4" description="" />
+     <symbol name="mhpmcounter6"         address="next"       size="4" description="" />
+     <symbol name="mhpmcounter7"         address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter8"  address="csreg:0xa08"       size="4" description="" />
+     <symbol name="mhpmcounter9"         address="next"       size="4" description="" />
+     <symbol name="mhpmcounter10"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter11"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter12"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter13"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter14"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter15"        address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter16" address="csreg:0xa10"       size="4" description="" />
+     <symbol name="mhpmcounter17"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter18"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter19"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter20"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter21"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter22"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter23"        address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter24" address="csreg:0xa18"       size="4" description="" />
+     <symbol name="mhpmcounter25"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter26"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter27"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter28"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter29"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter30"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter31"        address="next"       size="4" description="" />
+
+
+     <symbol name="mcycleh"       address="csreg:0xb80"       size="4" description="" />
+     <symbol name="minstreth"            address="next"       size="4" description="" />
+     <symbol name="mhpmcounter3h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter4h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter5h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter6h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter7h"        address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter8h" address="csreg:0xb88"       size="4" description="" />
+     <symbol name="mhpmcounter9h"         address="next"       size="4" description="" />
+     <symbol name="mhpmcounter10h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter11h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter12h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter13h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter14h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter15h"        address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter16h" address="csreg:0xb90"       size="4" description="" />
+     <symbol name="mhpmcounter17h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter18h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter19h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter20h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter21h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter22h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter23h"        address="next"       size="4" description="" />
+
+     <symbol name="mhpmcounter24h" address="csreg:0xb98"       size="4" description="" />
+     <symbol name="mhpmcounter25h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter26h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter27h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter28h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter29h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter30h"        address="next"       size="4" description="" />
+     <symbol name="mhpmcounter31h"        address="next"       size="4" description="" />
+
+
+     <symbol name="cycle"         address="csreg:0xc00"       size="4" description="" />
+     <symbol name="time"                 address="next"       size="4" description="" />
+     <symbol name="instret"              address="next"       size="4" description="" />
+     <symbol name="hpmcounter3"          address="next"       size="4" description="" />
+     <symbol name="hpmcounter4"          address="next"       size="4" description="" />
+     <symbol name="hpmcounter5"          address="next"       size="4" description="" />
+     <symbol name="hpmcounter6"          address="next"       size="4" description="" />
+     <symbol name="hpmcounter7"          address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter8"   address="csreg:0xc08"       size="4" description="" />
+     <symbol name="hpmcounter9"          address="next"       size="4" description="" />
+     <symbol name="hpmcounter10"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter11"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter12"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter13"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter14"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter15"         address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter16"  address="csreg:0xc10"       size="4" description="" />
+     <symbol name="hpmcounter17"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter18"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter19"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter20"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter21"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter22"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter23"         address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter24"  address="csreg:0xc18"       size="4" description="" />
+     <symbol name="hpmcounter25"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter26"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter27"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter28"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter29"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter30"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter31"         address="next"       size="4" description="" />
+
+     <symbol name="vl"            address="csreg:0xc20"       size="4" description="" />
+     <symbol name="vtype"                address="next"       size="4" description="" />
+     <symbol name="vlenb"                address="next"       size="4" description="" />
+
+
+     <symbol name="cycleh"        address="csreg:0xc80"       size="4" description="" />
+     <symbol name="timeh"                address="next"       size="4" description="" />
+     <symbol name="instreth"             address="next"       size="4" description="" />
+     <symbol name="hpmcounter3h"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter4h"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter5h"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter6h"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter7h"         address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter8h"  address="csreg:0xc88"       size="4" description="" />
+     <symbol name="hpmcounter9h"         address="next"       size="4" description="" />
+     <symbol name="hpmcounter10h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter11h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter12h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter13h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter14h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter15h"        address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter16h" address="csreg:0xc90"       size="4" description="" />
+     <symbol name="hpmcounter17h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter18h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter19h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter20h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter21h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter22h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter23h"        address="next"       size="4" description="" />
+
+     <symbol name="hpmcounter24h" address="csreg:0xc98"       size="4" description="" />
+     <symbol name="hpmcounter25h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter26h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter27h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter28h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter29h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter30h"        address="next"       size="4" description="" />
+     <symbol name="hpmcounter31h"        address="next"       size="4" description="" />
+
+
+     <symbol name="hgeip"         address="csreg:0xe12"       size="4" description="" />
+
+
+     <symbol name="mvendorid"     address="csreg:0xf11"       size="4" description="" />
+     <symbol name="marchid"       address="csreg:0xf12"       size="4" description="" />
+     <symbol name="mimpid"        address="csreg:0xf13"       size="4" description="" />
+     <symbol name="mhartid"       address="csreg:0xf14"       size="4" description="" />
+
+  </default_symbols>
+</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32G.pspec b/Ghidra/Processors/RISCV/data/languages/RV32G.pspec
deleted file mode 100644
index b3b2a71451..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV32G.pspec
+++ /dev/null
@@ -1,19 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="1"/>
-      <set name="RVA" val="1"/>
-      <set name="RVD" val="1"/>
-      <set name="RVF" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVM" val="1"/>
-      <set name="RVQ" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec
deleted file mode 100644
index 133923e1eb..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec
+++ /dev/null
@@ -1,20 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="1"/>
-      <set name="RVA" val="1"/>
-      <set name="RVC" val="1"/>
-      <set name="RVD" val="1"/>
-      <set name="RVF" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVM" val="1"/>
-      <set name="RVQ" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32I.pspec b/Ghidra/Processors/RISCV/data/languages/RV32I.pspec
deleted file mode 100644
index 7ece09e0e1..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV32I.pspec
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec
deleted file mode 100644
index 148daf445f..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="1"/>
-      <set name="RVC" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec
deleted file mode 100644
index b9f539d28a..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec
+++ /dev/null
@@ -1,16 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="1"/>
-      <set name="RVC" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVM" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64.pspec b/Ghidra/Processors/RISCV/data/languages/RV64.pspec
new file mode 100644
index 0000000000..91a024a8de
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/RV64.pspec
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+  <programcounter register="pc"/>
+  <context_data>
+    <context_set space="ram">
+      <set name="MXL" val="2"/>
+    </context_set>
+  </context_data>
+
+  <default_memory_blocks>
+    <memory_block name="csr" start_address="csreg:0x0" length="0x8000" initialized="false"/>
+  </default_memory_blocks>
+  
+  <!-- TODO: add include directive and move to shared include -->
+  <default_symbols>
+     <symbol name="ustatus"       address="csreg:0x000"       size="8" description="" />
+     <symbol name="fflags"        address="csreg:0x001"       size="8" description="" />
+     <symbol name="frm"           address="csreg:0x002"       size="8" description="" />
+     <symbol name="fcsr"          address="csreg:0x003"       size="8" description="" />
+     <symbol name="uie"           address="csreg:0x004"       size="8" description="" />
+     <symbol name="utvec"         address="csreg:0x005"       size="8" description="" />
+
+     <symbol name="vstart"        address="csreg:0x008"       size="8" description="" />
+     <symbol name="vxsat"         address="csreg:0x009"       size="8" description="" />
+     <symbol name="vxrm"          address="csreg:0x00a"       size="8" description="" />
+     <symbol name="vcsr"          address="csreg:0x00f"       size="8" description="" />
+
+
+     <symbol name="uscratch"      address="csreg:0x040"       size="8" description="" />
+     <symbol name="uepc"                 address="next"       size="8" description="" />
+     <symbol name="ucause"               address="next"       size="8" description="" />
+     <symbol name="utval"                address="next"       size="8" description="" />
+     <symbol name="uip"                  address="next"       size="8" description="" />
+
+
+     <symbol name="sstatus"       address="csreg:0x100"       size="8" description="" />
+     <symbol name="sedeleg"              address="next"       size="8" description="" />
+     <symbol name="sideleg"              address="next"       size="8" description="" />
+     <symbol name="sie"                  address="next"       size="8" description="" />
+     <symbol name="stvec"                address="next"       size="8" description="" />
+     <symbol name="scounteren"           address="next"       size="8" description="" />
+     
+
+     <symbol name="sscratch"      address="csreg:0x140"       size="8" description="" />
+     <symbol name="sepc"                 address="next"       size="8" description="" />
+     <symbol name="scause"               address="next"       size="8" description="" />
+     <symbol name="stval"                address="next"       size="8" description="" />
+     <symbol name="sip"                  address="next"       size="8" description="" />
+
+
+     <symbol name="satp"          address="csreg:0x180"       size="8" description="" />
+
+
+     <symbol name="vsstatus"      address="csreg:0x200"       size="8" description="" />
+     <symbol name="vsie"          address="csreg:0x204"       size="8" description="" />
+     <symbol name="vstvec"               address="next"       size="8" description="" />
+
+
+     <symbol name="vsscratch"     address="csreg:0x240"       size="8" description="" />
+     <symbol name="vsepc"                address="next"       size="8" description="" />
+     <symbol name="vscause"              address="next"       size="8" description="" />
+     <symbol name="vstval"               address="next"       size="8" description="" />
+     <symbol name="vsip"                 address="next"       size="8" description="" />
+
+
+     <symbol name="vsatp"         address="csreg:0x280"       size="8" description="" />
+
+
+     <symbol name="mstatus"       address="csreg:0x300"       size="8" description="" />
+     <symbol name="misa"                 address="next"       size="8" description="" />
+     <symbol name="medeleg"              address="next"       size="8" description="" />
+     <symbol name="mideleg"              address="next"       size="8" description="" />
+     <symbol name="mie"                  address="next"       size="8" description="" />
+     <symbol name="mtvec"                address="next"       size="8" description="" />
+     <symbol name="mcounteren"           address="next"       size="8" description="" />
+
+
+     <symbol name="mstatush"      address="csreg:0x310"       size="8" description="" />
+
+
+     <symbol name="mcountinhibit" address="csreg:0x320"       size="8" description="" />
+     <symbol name="mhpmevent3"    address="csreg:0x323"       size="8" description="" />
+     <symbol name="mhpmevent4"    address="csreg:0x324"       size="8" description="" />
+     <symbol name="mhpmevent5"    address="csreg:0x325"       size="8" description="" />
+     <symbol name="mhpmevent6"    address="csreg:0x326"       size="8" description="" />
+     <symbol name="mhpmevent7"    address="csreg:0x327"       size="8" description="" />
+
+     <symbol name="mhpmevent8"    address="csreg:0x328"       size="8" description="" />
+     <symbol name="mhpmevent9"    address="csreg:0x329"       size="8" description="" />
+     <symbol name="mhpmevent10"   address="csreg:0x32a"       size="8" description="" />
+     <symbol name="mhpmevent11"   address="csreg:0x32b"       size="8" description="" />
+     <symbol name="mhpmevent12"   address="csreg:0x32c"       size="8" description="" />
+     <symbol name="mhpmevent13"   address="csreg:0x32d"       size="8" description="" />
+     <symbol name="mhpmevent14"   address="csreg:0x32e"       size="8" description="" />
+     <symbol name="mhpmevent15"   address="csreg:0x32f"       size="8" description="" />
+
+     <symbol name="mhpmevent16"   address="csreg:0x330"       size="8" description="" />
+     <symbol name="mhpmevent17"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent18"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent19"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent20"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent21"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent22"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent23"          address="next"       size="8" description="" />
+
+     <symbol name="mhpmevent24"   address="csreg:0x338"       size="8" description="" />
+     <symbol name="mhpmevent25"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent26"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent27"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent28"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent29"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent30"          address="next"       size="8" description="" />
+     <symbol name="mhpmevent31"          address="next"       size="8" description="" />
+
+     <symbol name="mscratch"      address="csreg:0x340"       size="8" description="" />
+     <symbol name="mepc"          address="csreg:0x341"       size="8" description="" />
+     <symbol name="mcause"        address="csreg:0x342"       size="8" description="" />
+     <symbol name="mtval"         address="csreg:0x343"       size="8" description="" />
+     <symbol name="mip"           address="csreg:0x344"       size="8" description="" />
+
+     <symbol name="mtinst"        address="csreg:0x34a"       size="8" description="" />
+     <symbol name="mtval2"        address="csreg:0x34b"       size="8" description="" />
+
+
+     <symbol name="mbase"         address="csreg:0x380"       size="8" description="" />
+     <symbol name="mbound"        address="csreg:0x381"       size="8" description="" />
+     <symbol name="mibase"        address="csreg:0x382"       size="8" description="" />
+     <symbol name="mibound"       address="csreg:0x383"       size="8" description="" />
+     <symbol name="mdbase"        address="csreg:0x384"       size="8" description="" />
+     <symbol name="mdbound"       address="csreg:0x385"       size="8" description="" />
+
+
+     <symbol name="pmpcfg0"       address="csreg:0x3a0"       size="8" description="" />
+     <symbol name="pmpcfg1"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg2"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg3"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg4"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg5"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg6"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg7"              address="next"       size="8" description="" />
+
+     <symbol name="pmpcfg8"       address="csreg:0x3a8"       size="8" description="" />
+     <symbol name="pmpcfg9"              address="next"       size="8" description="" />
+     <symbol name="pmpcfg10"             address="next"       size="8" description="" />
+     <symbol name="pmpcfg11"             address="next"       size="8" description="" />
+     <symbol name="pmpcfg12"             address="next"       size="8" description="" />
+     <symbol name="pmpcfg13"             address="next"       size="8" description="" />
+     <symbol name="pmpcfg14"             address="next"       size="8" description="" />
+     <symbol name="pmpcfg15"             address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr0"      address="csreg:0x3b0"       size="8" description="" />
+     <symbol name="pmpaddr1"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr2"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr3"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr4"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr5"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr6"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr7"             address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr8"      address="csreg:0x3b8"       size="8" description="" />
+     <symbol name="pmpaddr9"             address="next"       size="8" description="" />
+     <symbol name="pmpaddr10"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr11"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr12"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr13"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr14"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr15"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr16"     address="csreg:0x3c0"       size="8" description="" />
+     <symbol name="pmpaddr17"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr18"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr19"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr20"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr21"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr22"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr23"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr24"     address="csreg:0x3c8"       size="8" description="" />
+     <symbol name="pmpaddr25"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr26"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr27"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr28"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr29"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr30"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr31"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr32"     address="csreg:0x3d0"       size="8" description="" />
+     <symbol name="pmpaddr33"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr34"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr35"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr36"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr37"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr38"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr39"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr40"     address="csreg:0x3d8"       size="8" description="" />
+     <symbol name="pmpaddr41"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr42"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr43"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr44"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr45"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr46"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr47"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr48"     address="csreg:0x3e0"       size="8" description="" />
+     <symbol name="pmpaddr49"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr50"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr51"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr52"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr53"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr54"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr55"            address="next"       size="8" description="" />
+
+     <symbol name="pmpaddr56"     address="csreg:0x3e8"       size="8" description="" />
+     <symbol name="pmpaddr57"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr58"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr59"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr60"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr61"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr62"            address="next"       size="8" description="" />
+     <symbol name="pmpaddr63"            address="next"       size="8" description="" />
+
+
+     <symbol name="scontext"      address="csreg:0x5a8"       size="8" description="" />
+
+
+     <symbol name="hstatus"       address="csreg:0x600"       size="8" description="" />
+     <symbol name="hedeleg"       address="csreg:0x602"       size="8" description="" />
+     <symbol name="hideleg"       address="csreg:0x603"       size="8" description="" />
+     <symbol name="hie"           address="csreg:0x604"       size="8" description="" />
+     <symbol name="htimedelta"    address="csreg:0x605"       size="8" description="" />
+     <symbol name="hcounteren"    address="csreg:0x606"       size="8" description="" />
+     <symbol name="hgeie"         address="csreg:0x607"       size="8" description="" />
+
+
+     <symbol name="htimedeltah"   address="csreg:0x615"       size="8" description="" />
+
+
+     <symbol name="htval"         address="csreg:0x643"       size="8" description="" />
+     <symbol name="hip"           address="csreg:0x644"       size="8" description="" />
+     <symbol name="hvip"          address="csreg:0x645"       size="8" description="" />
+
+     <symbol name="htinst"        address="csreg:0x64a"       size="8" description="" />
+
+
+     <symbol name="hgatp"         address="csreg:0x680"       size="8" description="" />
+
+
+     <symbol name="hcontext"      address="csreg:0x6a8"       size="8" description="" />
+
+
+     <symbol name="tselect"       address="csreg:0x7a0"       size="8" description="" />
+     <symbol name="tdata1"        address="csreg:0x7a1"       size="8" description="" />
+     <symbol name="tdata2"        address="csreg:0x7a2"       size="8" description="" />
+     <symbol name="tdata3"        address="csreg:0x7a3"       size="8" description="" />
+
+     <symbol name="mcontext"      address="csreg:0x7a8"       size="8" description="" />
+
+     <symbol name="dcsr"          address="csreg:0x7b0"       size="8" description="" />
+     <symbol name="dpc"           address="csreg:0x7b1"       size="8" description="" />
+     <symbol name="dscratch0"     address="csreg:0x7b2"       size="8" description="" />
+     <symbol name="dscratch1"     address="csreg:0x7b3"       size="8" description="" />
+
+
+     <symbol name="mcycle"        address="csreg:0xa00"       size="8" description="" />
+     <symbol name="minstret"      address="csreg:0xa02"       size="8" description="" />
+     <symbol name="mhpmcounter3"  address="csreg:0xa03"       size="8" description="" />
+     <symbol name="mhpmcounter4"         address="next"       size="8" description="" />
+     <symbol name="mhpmcounter5"         address="next"       size="8" description="" />
+     <symbol name="mhpmcounter6"         address="next"       size="8" description="" />
+     <symbol name="mhpmcounter7"         address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter8"  address="csreg:0xa08"       size="8" description="" />
+     <symbol name="mhpmcounter9"         address="next"       size="8" description="" />
+     <symbol name="mhpmcounter10"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter11"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter12"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter13"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter14"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter15"        address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter16" address="csreg:0xa10"       size="8" description="" />
+     <symbol name="mhpmcounter17"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter18"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter19"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter20"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter21"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter22"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter23"        address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter24" address="csreg:0xa18"       size="8" description="" />
+     <symbol name="mhpmcounter25"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter26"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter27"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter28"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter29"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter30"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter31"        address="next"       size="8" description="" />
+
+
+     <symbol name="mcycleh"       address="csreg:0xb80"       size="8" description="" />
+     <symbol name="minstreth"            address="next"       size="8" description="" />
+     <symbol name="mhpmcounter3h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter4h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter5h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter6h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter7h"        address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter8h" address="csreg:0xb88"       size="8" description="" />
+     <symbol name="mhpmcounter9h"         address="next"       size="8" description="" />
+     <symbol name="mhpmcounter10h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter11h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter12h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter13h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter14h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter15h"        address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter16h" address="csreg:0xb90"       size="8" description="" />
+     <symbol name="mhpmcounter17h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter18h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter19h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter20h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter21h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter22h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter23h"        address="next"       size="8" description="" />
+
+     <symbol name="mhpmcounter24h" address="csreg:0xb98"       size="8" description="" />
+     <symbol name="mhpmcounter25h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter26h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter27h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter28h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter29h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter30h"        address="next"       size="8" description="" />
+     <symbol name="mhpmcounter31h"        address="next"       size="8" description="" />
+
+
+     <symbol name="cycle"         address="csreg:0xc00"       size="8" description="" />
+     <symbol name="time"                 address="next"       size="8" description="" />
+     <symbol name="instret"              address="next"       size="8" description="" />
+     <symbol name="hpmcounter3"          address="next"       size="8" description="" />
+     <symbol name="hpmcounter4"          address="next"       size="8" description="" />
+     <symbol name="hpmcounter5"          address="next"       size="8" description="" />
+     <symbol name="hpmcounter6"          address="next"       size="8" description="" />
+     <symbol name="hpmcounter7"          address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter8"   address="csreg:0xc08"       size="8" description="" />
+     <symbol name="hpmcounter9"          address="next"       size="8" description="" />
+     <symbol name="hpmcounter10"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter11"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter12"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter13"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter14"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter15"         address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter16"  address="csreg:0xc10"       size="8" description="" />
+     <symbol name="hpmcounter17"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter18"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter19"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter20"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter21"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter22"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter23"         address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter24"  address="csreg:0xc18"       size="8" description="" />
+     <symbol name="hpmcounter25"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter26"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter27"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter28"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter29"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter30"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter31"         address="next"       size="8" description="" />
+
+     <symbol name="vl"            address="csreg:0xc20"       size="8" description="" />
+     <symbol name="vtype"                address="next"       size="8" description="" />
+     <symbol name="vlenb"                address="next"       size="8" description="" />
+
+
+     <symbol name="cycleh"        address="csreg:0xc80"       size="8" description="" />
+     <symbol name="timeh"                address="next"       size="8" description="" />
+     <symbol name="instreth"             address="next"       size="8" description="" />
+     <symbol name="hpmcounter3h"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter4h"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter5h"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter6h"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter7h"         address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter8h"  address="csreg:0xc88"       size="8" description="" />
+     <symbol name="hpmcounter9h"         address="next"       size="8" description="" />
+     <symbol name="hpmcounter10h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter11h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter12h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter13h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter14h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter15h"        address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter16h" address="csreg:0xc90"       size="8" description="" />
+     <symbol name="hpmcounter17h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter18h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter19h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter20h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter21h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter22h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter23h"        address="next"       size="8" description="" />
+
+     <symbol name="hpmcounter24h" address="csreg:0xc98"       size="8" description="" />
+     <symbol name="hpmcounter25h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter26h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter27h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter28h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter29h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter30h"        address="next"       size="8" description="" />
+     <symbol name="hpmcounter31h"        address="next"       size="8" description="" />
+
+
+     <symbol name="hgeip"         address="csreg:0xe12"       size="8" description="" />
+
+
+     <symbol name="mvendorid"     address="csreg:0xf11"       size="8" description="" />
+     <symbol name="marchid"       address="csreg:0xf12"       size="8" description="" />
+     <symbol name="mimpid"        address="csreg:0xf13"       size="8" description="" />
+     <symbol name="mhartid"       address="csreg:0xf14"       size="8" description="" />
+
+  </default_symbols>
+</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64G.pspec b/Ghidra/Processors/RISCV/data/languages/RV64G.pspec
deleted file mode 100644
index dcf939f3cf..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV64G.pspec
+++ /dev/null
@@ -1,19 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="2"/>
-      <set name="RVA" val="1"/>
-      <set name="RVD" val="1"/>
-      <set name="RVF" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVM" val="1"/>
-      <set name="RVQ" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec
deleted file mode 100644
index 2e75cb4f6a..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec
+++ /dev/null
@@ -1,20 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="2"/>
-      <set name="RVA" val="1"/>
-      <set name="RVC" val="1"/>
-      <set name="RVD" val="1"/>
-      <set name="RVF" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVM" val="1"/>
-      <set name="RVQ" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64I.pspec b/Ghidra/Processors/RISCV/data/languages/RV64I.pspec
deleted file mode 100644
index 726e53df3f..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV64I.pspec
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="2"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec
deleted file mode 100644
index 0944cda18a..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<processor_spec>
-  <programcounter register="pc"/>
-  <context_data>
-    <context_set space="ram">
-      <set name="MXL" val="2"/>
-      <set name="RVC" val="1"/>
-      <set name="RVH" val="1"/>
-      <set name="RVI" val="1"/>
-      <set name="RVS" val="1"/>
-      <set name="RVU" val="1"/>
-    </context_set>
-  </context_data>
-</processor_spec>
diff --git a/Ghidra/Processors/RISCV/data/languages/andestar_v5.instr.sinc b/Ghidra/Processors/RISCV/data/languages/andestar_v5.instr.sinc
new file mode 100644
index 0000000000..bb30a6333a
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/andestar_v5.instr.sinc
@@ -0,0 +1,607 @@
+#
+# AndeStar V5 extensions to base RISC-V architecture
+#
+
+#
+# ExecTable is loaded/overlayed on the memory segment
+# That is indexed by the E
+define space ExecTable type=ram_space size=2;
+
+@define CUSTOM0 "op0006=0b0001011"
+@define CUSTOM1 "op0006=0b0101011"
+@define CUSTOM2 "op0006=0b1011011"
+@define CUSTOM4 "op0006=0b1010111"
+
+simm18_lb: val is sop3131 & op1516 & op1719 & op2020 & op2130 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1) | op1414; ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_lh: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1); ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_lw: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<18) | (op1516<<16) | (op1719<<13) | (op2020<<12) | (op2130<<2); ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_ld: val is sop3131 & op1516 & op1719 & op2020 & op2122 & op2330 [ val = (sop3131<<19) | (op2122<<17) | (op1516<<15) | (op1719<<12) | (op2330<<3); ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_sb: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1) | op1414; ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_sh: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811  [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1); ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_sw: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0808 & op0911 [ val = (sop3131<<18) | (op0808<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0911<<2); ] {
+	export *[const]:$(XLEN) val;
+}
+
+simm18_sd: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0809 & op1011  [ val = (sop3131<<19) | (op0809<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op1011<<3); ] {
+	export *[const]:$(XLEN) val;
+}
+
+cimm: "#"^val is op2024 & op0707 [ val = op0707<<5 | op2024; ] {
+	# Note on 32-bit op0707 must be 0
+	export *[const]:$(XLEN) val;
+}
+
+cimm7: "#"^val is op3030 & op2024 & op0707 [ val = op3030<<6 | op0707<<5 | op2024; ] {
+	export *[const]:$(XLEN) val;
+}
+
+ra_imm10: dest is sop3131 & op2529 & op0811 [ dest = inst_start + (sop3131 << 10 | op2529<<5 | op0811<<1); ] {
+	export *[ram]:$(XLEN) dest;
+}
+
+
+:addigp rd,simm18_lb is simm18_lb & rd & op1213=1 & $(CUSTOM0)
+{
+	rd =  gp + simm18_lb;
+}
+
+:bbc rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=0 & op1214=0b111 & op0707=0 & $(CUSTOM2)
+{
+	tst:1 = (rs1 & (1 << cimm)) == 0;
+	if (tst) goto ra_imm10;
+}
+
+:bbs rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=1 & op1214=0b111 & op0707=0 & $(CUSTOM2)
+{
+	tst:1 = (rs1 & (1 << cimm)) == 1;
+	if (tst) goto ra_imm10;
+}
+
+:beqc rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b101 & $(CUSTOM2)
+{
+	tst:1 = rs1 == cimm7;
+	if (tst) goto ra_imm10;
+}
+
+:bnec rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b110 & $(CUSTOM2)
+{
+	tst:1 = rs1 != cimm7;
+	if (tst) goto ra_imm10;
+}
+
+msb: "#"^op2631 is op2631 { export *[const]:$(XLEN) op2631; }
+lsb: "#"^op2025 is op2025 { export *[const]:$(XLEN) op2025; }
+
+:bfos rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b011 & $(CUSTOM2)
+{
+	# msb==0  Rd[LSB] = sext(Rs1[0])
+	shift:$(XLEN) = ($(XLEN)*8-1);
+	val:$(XLEN) = (rs1 & 1 << shift) s>> (shift);
+	val = val << lsb;
+	rd = val;
+}
+
+:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2)
+{
+	# msb < lsb  Rd[LSB:MSB] = sext(Rs1[len-1:0])
+	len:$(XLEN) = lsb-msb+1;
+	shift:$(XLEN) = ($(XLEN)*8 - len);
+	val:$(XLEN) = (rs1 << shift) s>> shift;
+	val = val << msb;
+	rd = val;
+}
+
+:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2)
+{
+	# msb >= lsb  Rd[len-1:0] = sext(Rs1[MSB:LSB])
+	len:$(XLEN) = msb-lsb+1;
+	shift:$(XLEN) = ($(XLEN)*8 - msb - 1);
+	val:$(XLEN) = (rs1 << shift) s>> ($(XLEN)*8 - len);
+	rd = val;
+}
+
+:bfoz rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b010 & $(CUSTOM2)
+{
+	# msb==0  Rd[LSB] = zext(Rs1[0])
+	val:$(XLEN) = rs1 & 1;
+	val = val << lsb;
+	rd = val;
+}
+
+:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b010 & $(CUSTOM2)
+{
+	# msb < lsb  Rd[LSB:MSB] = zext(Rs1[len-1:0])
+	len:$(XLEN) = lsb-msb+1;
+	mask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len));
+	val:$(XLEN) = rs1 & mask;
+	val = val << msb;
+	rd = val;
+}
+
+:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & op1214=0b010 & $(CUSTOM2)
+{
+	# msb >= lsb  Rd[len-1:0] = zext(Rs1[MSB:LSB])
+	len:$(XLEN) = msb-lsb+1;
+	mask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len)) << lsb;
+	val:$(XLEN) = rs1 & mask;
+	val = val >> lsb;
+	rd = val;
+}
+
+
+
+:lea.h rd,rs1,rs2 is op2531=0b0000101 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + rs2 * 2;
+	rd = ea;
+}
+
+:lea.w rd,rs1,rs2 is op2531=0b0000110 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + rs2 * 4;
+	rd = ea;
+}
+
+:lea.d rd,rs1,rs2 is op2531=0b0000111 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + rs2 * 8;
+	rd = ea;
+}
+
+:lea.b.ze rd,rs1,rs2 is op2531=0b0001000 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + zext(rs2:4);
+	rd = ea;
+}
+
+:lea.h.ze rd,rs1,rs2 is op2531=0b0001001 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + zext(rs2:4) * 2;
+	rd = ea;
+}
+
+:lea.w.ze rd,rs1,rs2 is op2531=0b0001010 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + zext(rs2:4) * 4;
+	rd = ea;
+}
+
+:lea.d.ze rd,rs1,rs2 is op2531=0b0001011 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2)
+{
+	local ea:$(XLEN) = rs1 + zext(rs2:4) * 8;
+	rd = ea;
+}
+
+:lbgp rd,"["^simm18_lb^"]" is simm18_lb & rd & op1213=0 & $(CUSTOM0)
+{
+	local ea:$(XLEN) = gp + simm18_lb;
+	rd = sext(*[ram]:1 ea);
+}
+
+:lbugp rd,"["^simm18_lb^"]" is simm18_lb & rd & op1213=2 & $(CUSTOM0)
+{
+	local ea:$(XLEN) = gp + simm18_lb;
+	rd = zext(*[ram]:1 ea);
+}
+
+:lhgp rd,"["^simm18_lh^"]" is simm18_lh & rd & op1214=1 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_lh;
+	rd = sext(*[ram]:2 ea);
+}
+
+:lhugp rd,"["^simm18_lh^"]" is simm18_lh & rd & op1214=5 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_lh;
+	rd = zext(*[ram]:2 ea);
+}
+
+:lwgp rd,"["^simm18_lw^"]" is simm18_lw & rd & op1214=2 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_lw;
+	rd = sext(*[ram]:4 ea);
+}
+
+:lwugp rd,"["^simm18_lw^"]" is simm18_lw & rd & op1214=6 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_lw;
+	rd = zext(*[ram]:4 ea);
+}
+
+:ldgp rd,"["^simm18_ld^"]" is simm18_ld & rd & op1214=3 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_ld;
+	rd = *[ram]:8 ea;
+}
+
+:sbgp rs2,"["^simm18_sb^"]" is simm18_sb & rs2 & op1213=3 & $(CUSTOM0)
+{
+	local ea:$(XLEN) = gp + simm18_sb;
+	*[ram]:1 ea = rs2[0,8];
+}
+
+:shgp rs2,"["^simm18_sh^"]" is simm18_sh & rs2 & op1214=0 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_sh;
+	*[ram]:2 ea = rs2[0,16];
+}
+
+:swgp rs2,"["^simm18_sw^"]" is simm18_sw & rs2 & op1214=4 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_sw;
+	*[ram]:4 ea = rs2[0,32];
+}
+
+:sdgp rs2,"["^simm18_sd^"]" is simm18_sd & rs2 & op1214=7 & $(CUSTOM1)
+{
+	local ea:$(XLEN) = gp + simm18_sd;
+	*[ram]:8 ea = rs2;
+}
+
+
+:ffb rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010000 & op1214=0 & $(CUSTOM2) {
+@if XLEN == "4"
+	m1:1 = (rs1[0,8]  == rs2[0,8]);
+	m2:1 = (rs1[8,8]  == rs2[0,8]);
+	m3:1 = (rs1[16,8] == rs2[0,8]);
+	m4:1 = (rs1[24,8] == rs2[0,8]);
+	rd = -4;
+	if (m1) goto inst_next;
+	rd = -3;
+	if (m2) goto inst_next;
+	rd = -2;
+	if (m3) goto inst_next;
+	rd = -1;
+	if (m4) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
+@else
+   	m1:1 = (rs1[0,8]  == rs2[0,8]);
+	m2:1 = (rs1[8,8]  == rs2[0,8]);
+	m3:1 = (rs1[16,8] == rs2[0,8]);
+	m4:1 = (rs1[24,8] == rs2[0,8]);
+	m5:1 = (rs1[32,8] == rs2[0,8]);
+	m6:1 = (rs1[40,8] == rs2[0,8]);
+	m7:1 = (rs1[48,8] == rs2[0,8]);
+	m8:1 = (rs1[56,8] == rs2[0,8]);
+	rd = -8;
+	if (m1) goto inst_next;
+	rd = -7;
+	if (m2) goto inst_next;
+	rd = -6;
+	if (m3) goto inst_next;
+	rd = -5;
+	if (m4) goto inst_next;
+	rd = -4;
+	if (m5) goto inst_next;
+	rd = -3;
+	if (m6) goto inst_next;
+	rd = -2;
+	if (m7) goto inst_next;
+	rd = -1;
+	if (m8) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);
+@endif
+}
+
+:ffzmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010001 & op1214=0 & $(CUSTOM2) {
+@if XLEN == "4"
+	m1:1 = (rs1[0,8]==0)  | (rs1[0,8] == rs2[0,8]);
+	m2:1 = (rs1[8,8]==0)  | (rs1[8,8] == rs2[8,8]);
+	m3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]);
+	m4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]);
+	rd = -4;
+	if (m1) goto inst_next;
+	rd = -3;
+	if (m2) goto inst_next;
+	rd = -2;
+	if (m3) goto inst_next;
+	rd = -1;
+	if (m4) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
+@else
+   	m1:1 = (rs1[0,8]==0)  | (rs1[0,8]  == rs2[0,8]);
+	m2:1 = (rs1[8,8]==0)  | (rs1[8,8]  == rs2[8,8]);
+	m3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]);
+	m4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]);
+	m5:1 = (rs1[32,8]==0) | (rs1[32,8] == rs2[32,8]);
+	m6:1 = (rs1[40,8]==0) | (rs1[40,8] == rs2[40,8]);
+	m7:1 = (rs1[48,8]==0) | (rs1[48,8] == rs2[48,8]);
+	m8:1 = (rs1[56,8]==0) | (rs1[56,8] == rs2[56,8]);
+	rd = -8;
+	if (m1) goto inst_next;
+	rd = -7;
+	if (m2) goto inst_next;
+	rd = -6;
+	if (m3) goto inst_next;
+	rd = -5;
+	if (m4) goto inst_next;
+	rd = -4;
+	if (m5) goto inst_next;
+	rd = -3;
+	if (m6) goto inst_next;
+	rd = -2;
+	if (m7) goto inst_next;
+	rd = -1;
+	if (m8) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);
+@endif
+}
+
+:ffmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010010 & op1214=0 & $(CUSTOM2) {
+@if XLEN == "4"
+	m1:1 = (rs1[0,8]  != rs2[0,8]);
+	m2:1 = (rs1[8,8]  != rs2[8,8]);
+	m3:1 = (rs1[16,8] != rs2[16,8]);
+	m4:1 = (rs1[24,8] != rs2[24,8]);
+	rd = -4;
+	if (m1) goto inst_next;
+	rd = -3;
+	if (m2) goto inst_next;
+	rd = -2;
+	if (m3) goto inst_next;
+	rd = -1;
+	if (m4) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
+@else
+   	m1:1 = (rs1[0,8]  != rs2[0,8]);
+	m2:1 = (rs1[8,8]  != rs2[8,8]);
+	m3:1 = (rs1[16,8] != rs2[16,8]);
+	m4:1 = (rs1[24,8] != rs2[24,8]);
+	m5:1 = (rs1[32,8] != rs2[32,8]);
+	m6:1 = (rs1[40,8] != rs2[40,8]);
+	m7:1 = (rs1[48,8] != rs2[48,8]);
+	m8:1 = (rs1[56,8] != rs2[56,8]);
+	rd = -8;
+	if (m1) goto inst_next;
+	rd = -7;
+	if (m2) goto inst_next;
+	rd = -6;
+	if (m3) goto inst_next;
+	rd = -5;
+	if (m4) goto inst_next;
+	rd = -4;
+	if (m5) goto inst_next;
+	rd = -3;
+	if (m6) goto inst_next;
+	rd = -2;
+	if (m7) goto inst_next;
+	rd = -1;
+	if (m8) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);
+@endif
+}
+
+:flmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010011 & op1214=0 & $(CUSTOM2) {
+@if XLEN == "4"
+	m1:1 = (rs1[0,8]  != rs2[0,8]);
+	m2:1 = (rs1[8,8]  != rs2[8,8]);
+	m3:1 = (rs1[16,8] != rs2[16,8]);
+	m4:1 = (rs1[24,8] != rs2[24,8]);
+	rd = -1;
+	if (m4) goto inst_next;
+	rd = -2;
+	if (m3) goto inst_next;
+	rd = -3;
+	if (m2) goto inst_next;
+	rd = -4;
+	if (m1) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
+@else
+   	m1:1 = (rs1[0,8]  != rs2[0,8]);
+	m2:1 = (rs1[8,8]  != rs2[8,8]);
+	m3:1 = (rs1[16,8] != rs2[16,8]);
+	m4:1 = (rs1[24,8] != rs2[24,8]);
+	m5:1 = (rs1[32,8] != rs2[32,8]);
+	m6:1 = (rs1[40,8] != rs2[40,8]);
+	m7:1 = (rs1[48,8] != rs2[48,8]);
+	m8:1 = (rs1[56,8] != rs2[56,8]);
+	rd = -1;
+	if (m8) goto inst_next;
+	rd = -2;
+	if (m7) goto inst_next;
+	rd = -3;
+	if (m6) goto inst_next;
+	rd = -4;
+	if (m5) goto inst_next;
+	rd = -5;
+	if (m4) goto inst_next;
+	rd = -6;
+	if (m3) goto inst_next;
+	rd = -7;
+	if (m2) goto inst_next;
+	rd = -8;
+	if (m1) goto inst_next;
+	rd = 0;
+	# choosery method
+	# rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1);
+@endif
+}
+
+imm11_exec: val is cop1212 & cop1011 & cop0909 & cop0808 & cop0506 & cop0404 & cop0303 & cop0202
+  [ val = (cop0808<<11)|(cop1212<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] {
+  	export *[ExecTable]:2 val;
+}
+
+#
+# Code Dense (CoDense) extension
+
+
+#100 imm[10|4:3|8] imm[11] 0 imm[7:6|2|9|5] 00
+:exec.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0707=0 & cop0001=0 {
+	ExecRetAddr = inst_next;
+	goto imm11_exec;
+}
+
+:ex9.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0708=0 & cop0001=0 {
+	ExecRetAddr = inst_next;
+	goto imm11_exec;
+}
+
+#
+# alternate version of EXEC.IT when mmsc_cfb.ECDV=1
+#
+imm11_nexec: val is cop1011 & cop0909 & cop0808 & cop0707 & cop0506 & cop0404 & cop0303 & cop0202
+  [ val = (cop0808<<11)|(cop0707<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] {
+  	export *[ExecTable]:2 val;
+}
+
+# 100 1 imm[4:3|8] imm[11] imm[10] imm[7:6|2|9|5] 00
+:nexec.it imm11_nexec is ecdv=1 & cop1315=4 & cop1212=1 & imm11_nexec & cop0001=0 {
+	ExecRetAddr = inst_next;
+	goto imm11_nexec;
+}
+
+#
+# INT4 vector load extension
+#
+define pcodeop vln8;
+
+:vln8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00010 & op1214=0b100 & $(CUSTOM2) {
+	# TODO load 32 4bit values, possibly sext by vm into 32 8-bit vector registers
+	val:$(VLEN) = *[ram]:$(VLEN) rs1;
+	vd = vln8(val);
+	build vm;
+}
+
+:vlnu8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00011 & op1214=0b100 & $(CUSTOM2) {
+	# TODO load 32 4bit values, possibly zext by vm into 32 8-bit vector registers
+	val:$(VLEN) = *[ram]:$(VLEN) rs1;
+	vd = vln8(val);
+	build vm;
+}
+
+
+#
+# bfloat16 conversion extension
+#
+define pcodeop fcvt.s.bf16;
+
+:fcvt.s.bf16   frd,frs2  is frd & frs2 & op2531=0 & op1519=0b00010 & op1214=0b100 & $(CUSTOM2) {
+	frd = fcvt.s.bf16(frs2);
+}
+
+define pcodeop fcvt.bf16.s;
+
+:fcvt.bf16.s   frd,frs2  is frd & frs2 & op2531=0 & op1519=0b00011 & op1214=0b100 & $(CUSTOM2) {
+	frd = fcvt.bf16.s(frs2);
+}
+
+#
+# Vector BFloat16 conversion extension
+#
+
+define pcodeop vfwcvt.s.bf16;
+
+:vfwcvt.s.bf16 vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00000 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfwcvt.s.bf16(vs2);
+}
+
+define pcodeop vfncvt.bf16.s;
+
+:vfncvt.bf16.s vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00001 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfncvt.bf16.s(vs2);
+}
+
+define pcodeop vfpmadt.vf;
+
+:vfpmadt.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000010 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfpmadt.vf(rs1,vs2);
+	build vm;
+}
+
+define pcodeop vfpmadb.vf;
+
+:vfpmadb.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000011 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfpmadb.vf(rs1,vs2);
+	build vm;
+}
+
+define pcodeop vd4dots.vv;
+
+:vd4dots.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000100 & op1214=0b100 & $(CUSTOM2) {
+	vd = vd4dots.vv(vs1,vs2);
+	build vm;
+}
+
+define pcodeop vd4dotu.vv;
+
+:vd4dotu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000111 & op1214=0b100 & $(CUSTOM2) {
+	vd = vd4dotu.vv(vs1,vs2);
+	build vm;
+}
+
+define pcodeop vd4dotsu.vv;
+
+:vd4dotsu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000101 & op1214=0b100 & $(CUSTOM2) {
+	vd = vd4dotsu.vv(vs1,vs2);
+	build vm;
+}
+
+define pcodeop vle4.v;
+
+:vle4.v vd,(rs1) is vd & rs1 & op2631=0b000001 & op2525=1 & op2024=0b00000 & op1214=0b100 & $(CUSTOM2) {
+	val:$(VLEN) = *[ram]:$(VLEN) rs1;
+	vd = vle4.v(val);
+}
+
+define pcodeop vfwcvt.f.n.v;
+
+:vfwcvt.f.n.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00100 & op1214=0b100 & $(CUSTOM2) {
+    vd = vfwcvt.f.n.v(vs2);
+    build vm;
+}
+
+define pcodeop vfwcvt.f.nu.v;
+
+:vfwcvt.f.nu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00101 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfwcvt.f.nu.v(vs2);
+	build vm;
+}
+
+define pcodeop vfwcvt.f.b.v;
+
+:vfwcvt.f.b.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00110 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfwcvt.f.b.v(vs2);
+	build vm;
+}
+
+define pcodeop vfwcvt.f.bu.v;
+
+:vfwcvt.f.bu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00111 & op1214=0b100 & $(CUSTOM2) {
+	vd = vfwcvt.f.bu.v(vs2);
+	build vm;
+}
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/andestar_v5.ldefs b/Ghidra/Processors/RISCV/data/languages/andestar_v5.ldefs
new file mode 100644
index 0000000000..7d45531bcd
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/andestar_v5.ldefs
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<language_definitions>
+
+  <language processor="RISCV"
+            endian="little"
+            size="32"
+            variant="AndeStar_v5"
+            version="1.4"
+            slafile="andestar_v5.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:AndeStar_v5">
+    <description>AndeStar v5 RISC-V based 32 little default</description>
+    <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+  </language>
+  
+</language_definitions>
diff --git a/Ghidra/Processors/RISCV/data/languages/andestar_v5.slaspec b/Ghidra/Processors/RISCV/data/languages/andestar_v5.slaspec
new file mode 100644
index 0000000000..1720753a71
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/andestar_v5.slaspec
@@ -0,0 +1,36 @@
+define endian=little;
+
+@define XLEN 4
+@define XLEN2 8
+@define FLEN 8
+@define CONTEXTLEN 8
+
+@define ADDRSIZE "32"
+@define FPSIZE "64"
+
+@include "riscv.reg.sinc"
+
+define context CONTEXT
+    isExecInstr=(32,32)
+    phase=(33,33)
+    ecdv=(34,34)
+;
+
+@include "riscv.table.sinc"
+
+
+# artificial return register
+
+define register offset=0x6000 size=4 [ ExecRetAddr ];
+
+Dest: is epsilon { export *[ram]:1 ExecRetAddr; }
+
+:^instruction is phase=0 & isExecInstr=1 & instruction [ phase=1; ] { build instruction; local dest:$(XLEN) = ExecRetAddr; goto [dest]; }
+:^instruction is phase=0 & isExecInstr=0 & instruction [ phase=1; ] { build instruction; }
+
+with : phase=1 {
+@include "riscv.instr.sinc"
+
+@include "andestar_v5.instr.sinc"
+
+}
diff --git a/Ghidra/Processors/RISCV/data/languages/old/riscv_deprecated.ldefs b/Ghidra/Processors/RISCV/data/languages/old/riscv_deprecated.ldefs
new file mode 100644
index 0000000000..0002af5a63
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/old/riscv_deprecated.ldefs
@@ -0,0 +1,150 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<language_definitions>
+
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="64"
+            variant="RV64I"
+            version="1.4"
+            slafile="riscv.lp64d.sla"
+            processorspec="RV64.pspec"
+            id="RISCV:LE:64:RV64I">
+    <description>RISC-V 64 little base</description>
+    <compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv64"/>
+    <external_name tool="qemu" name="qemu-riscv64"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="64"
+            variant="RV64IC"
+            version="1.4"
+            slafile="riscv.lp64d.sla"
+            processorspec="RV64.pspec"
+            id="RISCV:LE:64:RV64IC">
+    <description>RISC-V 64 little base compressed</description>
+    <compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv64"/>
+    <external_name tool="qemu" name="qemu-riscv64"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="64"
+            variant="RV64G"
+            version="1.4"
+            slafile="riscv.lp64d.sla"
+            processorspec="RV64.pspec"
+            id="RISCV:LE:64:RV64G">
+    <description>RISC-V 64 little general purpose</description>
+    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv64"/>
+    <external_name tool="qemu" name="qemu-riscv64"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="64"
+            variant="RV64GC"
+            version="1.4"
+            slafile="riscv.lp64d.sla"
+            processorspec="RV64.pspec"
+            id="RISCV:LE:64:RV64GC">
+    <description>RISC-V 64 little general purpose compressed</description>
+    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
+    <external_name tool="gnu" name="riscv:rv64"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
+    <external_name tool="qemu" name="qemu-riscv64"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="32"
+            variant="RV32I"
+            version="1.4"
+            slafile="riscv.ilp32d.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:RV32I">
+    <description>RISC-V 32 little base</description>
+    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="32"
+            variant="RV32IC"
+            version="1.4"
+            slafile="riscv.ilp32d.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:RV32IC">
+    <description>RISC-V 32 little base compressed</description>
+    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
+  </language>
+    <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="32"
+            variant="RV32IMC"
+            version="1.4"
+            slafile="riscv.ilp32d.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:RV32IMC">
+    <description>RISC-V 32 little base compressed</description>
+    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="32"
+            variant="RV32G"
+            version="1.4"
+            slafile="riscv.ilp32d.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:RV32G">
+    <description>RISC-V 32 little general purpose</description>
+    <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
+  </language>
+  <language processor="RISCV"
+            deprecated="true"
+            endian="little"
+            size="32"
+            variant="RV32GC"
+            version="1.4"
+            slafile="riscv.ilp32d.sla"
+            processorspec="RV32.pspec"
+            id="RISCV:LE:32:RV32GC">
+    <description>RISC-V 32 little general purpose compressed</description>
+    <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
+    <external_name tool="gnu" name="riscv:rv32"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
+    <external_name tool="qemu" name="qemu-riscv32"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
+  </language> 
+  
+</language_definitions>
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
index b29608f285..a38313fe23 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
@@ -2,71 +2,109 @@
 
 
 # csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) 
-:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519
+:csrc csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0
 {
 	local tmprs1:$(XLEN) = rs1;
 	local oldcsr:$(XLEN) = csr:$(XLEN);
-	rdDst = oldcsr;
-	local tmp:$(XLEN) = op1519;
-	if (tmp == 0) goto inst_next;
 	local newcsr:$(XLEN) = oldcsr & ~tmprs1;
 	csr = newcsr;
 }
 
+# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) 
+:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711
+{
+	local tmprs1:$(XLEN) = rs1;
+	local oldcsr:$(XLEN) = csr:$(XLEN);
+	local newcsr:$(XLEN) = oldcsr & ~tmprs1;
+	csr = newcsr;
+	rdDst = oldcsr;
+}
+
+# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) 
+:csrci csr,op1519 is op1519 & op0711=0 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
+{
+	local oldcsr:$(XLEN) = csr:$(XLEN);
+	local tmp:$(XLEN) = op1519;
+	csr = oldcsr & ~tmp;
+}
+
 
 # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) 
 :csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
-	rdDst = oldcsr;
 	local tmp:$(XLEN) = op1519;
-	if (tmp == 0) goto inst_next;
-	csr = csr & ~tmp;
+	csr = oldcsr & ~tmp;
+	rdDst = oldcsr;
 }
 
 
 # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
-:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519
+:csrr rdDst,csr is csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711
 {
-	local tmprs1 = rs1;
-	local oldcsr:$(XLEN) = csr:$(XLEN);
-	rdDst = oldcsr;
-	local tmp:$(XLEN) = op1519;
-	if (tmp == 0) goto inst_next;
-	csr = csr | tmprs1;
+	rdDst = csr:$(XLEN);
 }
 
+# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
+:csrs csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711=0
+{
+	local oldcsr:$(XLEN) = csr:$(XLEN);
+	csr = oldcsr | rs1;
+}
+
+# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
+:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711
+{
+	local oldcsr:$(XLEN) = csr:$(XLEN);
+	csr = oldcsr | rs1;
+	rdDst  = oldcsr;
+}
 
 # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) 
-:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
+:csrsi csr,op1519 is op1519 & csr & op0711=0 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
-	rdDst = oldcsr;
 	local tmp:$(XLEN) = op1519;
-	if (tmp == 0) goto inst_next;
-	csr = csr | tmp;
+	csr = oldcsr | tmp;
 }
 
+# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) 
+:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711
+{
+	local oldcsr:$(XLEN) = csr:$(XLEN);
+	local tmp:$(XLEN) = op1519;
+	csr = oldcsr | tmp;
+	rdDst = oldcsr;
+}
+
+# csrw d,E,s 00001073 0000707f SIMPLE (0, 0) 
+:csrw csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & r0711=0
+{
+	csr = rs1;
+}
 
 # csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) 
-:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519
+:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1
 {
 	local tmprs1:$(XLEN) = rs1;
 	local oldcsr:$(XLEN) = csr:$(XLEN);
-	local tmp:$(XLEN) = op1519;
 	csr = tmprs1;
-	if (tmp == 0) goto inst_next;
 	rdDst = oldcsr;
 }
 
+# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) 
+:csrwi csr,op1519 is op1519 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711=0
+{
+	local val:$(XLEN) = op1519;
+	csr = val;
+}
 
 # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) 
-:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5
+:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
-	local tmp:$(XLEN) = op1519;
-	csr = tmp;
-	if (tmp == 0) goto inst_next;
+	local val:$(XLEN) = op1519;
+	csr = val;
 	rdDst = oldcsr;
 }
 
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
index 81dbf0589f..ee9976d0fb 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
@@ -4,8 +4,7 @@ define endian=little;
 @define XLEN2 8
 @define FLEN 8
 
-@define MXLEN_1 31
-@define MXLEN_2 30
+@define CONTEXTLEN 4
 
 @define ADDRSIZE "32"
 @define FPSIZE "64"
@@ -13,3 +12,6 @@ define endian=little;
 @include "riscv.reg.sinc"
 @include "riscv.table.sinc"
 @include "riscv.instr.sinc"
+
+# include placeholder decode for *some* custom instructions
+@include "riscv.custom.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
index 743bdbaf39..15a1daa1be 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
@@ -27,7 +27,6 @@
 @include "riscv.rv64m.sinc"
 @include "riscv.rv64b.sinc"
 @include "riscv.rv64p.sinc"
-@include "riscv.rv64k.sinc"
 
 @if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128"
 @include "riscv.rv64f.sinc"
@@ -48,8 +47,6 @@
 @include "riscv.rvv.sinc"
 @include "riscv.zi.sinc"
 
-@include "riscv.custom.sinc"
-
 # todos that may be possible, mostly just artifacts from my
 # script to generate the initial SELIGH
 
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
index 144a7be1cf..346f7d6fa7 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
@@ -1,164 +1,30 @@
 <?xml version="1.0" encoding="UTF-8"?>
 
 <language_definitions>
+
+  <language processor="RISCV"
+            endian="little"
+            size="64"
+            variant="default"
+            version="1.4"
+            slafile="riscv.lp64d.sla"
+            processorspec="RV64.pspec"
+            id="RISCV:LE:64:default">
+    <description>RISC-V 64 little default</description>
+    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
+    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
+    <external_name tool="gnu" name="riscv:rv64"/>
+    <external_name tool="qemu" name="qemu-riscv64"/>
+    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
+  </language>
   
-  <language processor="RISCV"
-            endian="little"
-            size="64"
-            variant="RV64I"
-            version="1.3"
-            slafile="riscv.lp64d.sla"
-            processorspec="RV64I.pspec"
-            id="RISCV:LE:64:RV64I">
-    <description>RISC-V 64 little base</description>
-    <compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv64"/>
-    <external_name tool="qemu" name="qemu-riscv64"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="64"
-            variant="RV64IC"
-            version="1.3"
-            slafile="riscv.lp64d.sla"
-            processorspec="RV64IC.pspec"
-            id="RISCV:LE:64:RV64IC">
-    <description>RISC-V 64 little base compressed</description>
-    <compiler name="gcc" spec="riscv64.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv64"/>
-    <external_name tool="qemu" name="qemu-riscv64"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="64"
-            variant="RV64G"
-            version="1.3"
-            slafile="riscv.lp64d.sla"
-            processorspec="RV64G.pspec"
-            id="RISCV:LE:64:RV64G">
-    <description>RISC-V 64 little general purpose</description>
-    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv64"/>
-    <external_name tool="qemu" name="qemu-riscv64"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="64"
-            variant="RV64GC"
-            version="1.3"
-            slafile="riscv.lp64d.sla"
-            processorspec="RV64GC.pspec"
-            id="RISCV:LE:64:RV64GC">
-    <description>RISC-V 64 little general purpose compressed</description>
-    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
-    <external_name tool="gnu" name="riscv:rv64"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
-    <external_name tool="qemu" name="qemu-riscv64"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="64"
-            variant="default"
-            version="1.3"
-            slafile="riscv.lp64d.sla"
-            processorspec="RV64GC.pspec"
-            id="RISCV:LE:64:default">
-    <description>RISC-V 32 little default</description>
-    <compiler name="gcc" spec="riscv64-fp.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv64.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv64"/>
-    <external_name tool="qemu" name="qemu-riscv64"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv64"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="32"
-            variant="RV32I"
-            version="1.3"
-            slafile="riscv.ilp32d.sla"
-            processorspec="RV32I.pspec"
-            id="RISCV:LE:32:RV32I">
-    <description>RISC-V 32 little base</description>
-    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv32"/>
-    <external_name tool="qemu" name="qemu-riscv32"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="32"
-            variant="RV32IC"
-            version="1.3"
-            slafile="riscv.ilp32d.sla"
-            processorspec="RV32IC.pspec"
-            id="RISCV:LE:32:RV32IC">
-    <description>RISC-V 32 little base compressed</description>
-    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv32"/>
-    <external_name tool="qemu" name="qemu-riscv32"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
-  </language>
-    <language processor="RISCV"
-            endian="little"
-            size="32"
-            variant="RV32IMC"
-            version="1.3"
-            slafile="riscv.ilp32d.sla"
-            processorspec="RV32IMC.pspec"
-            id="RISCV:LE:32:RV32IMC">
-    <description>RISC-V 32 little base compressed</description>
-    <compiler name="gcc" spec="riscv32.cspec" id="gcc"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
-    <external_name tool="gnu" name="riscv:rv32"/>
-    <external_name tool="qemu" name="qemu-riscv32"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="32"
-            variant="RV32G"
-            version="1.3"
-            slafile="riscv.ilp32d.sla"
-            processorspec="RV32G.pspec"
-            id="RISCV:LE:32:RV32G">
-    <description>RISC-V 32 little general purpose</description>
-    <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
-    <external_name tool="gnu" name="riscv:rv32"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
-    <external_name tool="qemu" name="qemu-riscv32"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
-  </language>
-  <language processor="RISCV"
-            endian="little"
-            size="32"
-            variant="RV32GC"
-            version="1.3"
-            slafile="riscv.ilp32d.sla"
-            processorspec="RV32GC.pspec"
-            id="RISCV:LE:32:RV32GC">
-    <description>RISC-V 32 little general purpose compressed</description>
-    <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
-    <external_name tool="gnu" name="riscv:rv32"/>
-    <external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
-    <external_name tool="qemu" name="qemu-riscv32"/>
-    <external_name tool="qemu_system" name="qemu-system-riscv32"/>
-  </language>
   <language processor="RISCV"
             endian="little"
             size="32"
             variant="default"
-            version="1.3"
+            version="1.4"
             slafile="riscv.ilp32d.sla"
-            processorspec="RV32GC.pspec"
+            processorspec="RV32.pspec"
             id="RISCV:LE:32:default">
     <description>RISC-V 32 little default</description>
     <compiler name="gcc" spec="riscv32-fp.cspec" id="gcc"/>
@@ -167,5 +33,5 @@
     <external_name tool="qemu" name="qemu-riscv32"/>
     <external_name tool="qemu_system" name="qemu-system-riscv32"/>
   </language>
-  
+
 </language_definitions>
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
index c07b5382ed..f1d11a233a 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
@@ -4,8 +4,7 @@ define endian=little;
 @define XLEN2 16
 @define FLEN 8
 
-@define MXLEN_1 63
-@define MXLEN_2 62
+@define CONTEXTLEN 4
 
 @define ADDRSIZE "64"
 @define FPSIZE "64"
@@ -13,3 +12,6 @@ define endian=little;
 @include "riscv.reg.sinc"
 @include "riscv.table.sinc"
 @include "riscv.instr.sinc"
+
+@include "riscv.rv64k.sinc"    # current encoding is in custom space
+@include "riscv.custom.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
index 5b09d07e43..91ede6e4ae 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
@@ -4,6 +4,10 @@ define alignment=2;
 define space ram type=ram_space size=$(XLEN) default;
 define space register type=register_space size=4;
 
+define space csreg type=ram_space size=2 wordsize=$(XLEN); # really 12bit space, for 4096 registers
+
+define register offset=0x100 size=$(CONTEXTLEN) [ CONTEXT ];
+
 define register offset=0x1000 size=$(XLEN) [ pc ];
 
 
@@ -51,530 +55,14 @@ define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2  ft3  ft4 ft5 ft6  ft7
 				       	     fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
 
 #TODO  fix
-@define VLEN "256"
+@define VLEN "32"
 define register offset=0x4000 size=$(VLEN) [ v0  v1  v2  v3  v4  v5  v6  v7
        			      		     v8  v9  v10 v11 v12 v13 v14 v15
 					     v16 v17 v18 v19 v20 v21 v22 v23
 					     v24 v25 v26 v27 v28 v29 v30 v31 ];
 
-
-define register offset=0x90000000 size=$(XLEN) [
- ustatus fflags frm fcsr uie utvec csr006 csr007
- vstart vxsat  vxrm   csr00b csr00c csr00d csr00e vcsr
- csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017
- csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f
- csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027
- csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f
- csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037
- csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f
- uscratch uepc ucause utval uip csr045 csr046 csr047
- csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f
- csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057
- csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f
- csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067
- csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f
- csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077
- csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f
- csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087
- csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f
- csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097
- csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f
- csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7
- csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af
- csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7
- csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf
- csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7
- csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf
- csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7
- csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df
- csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7
- csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef
- csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7
- csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff
- sstatus csr101 sedeleg sideleg sie stvec scounteren csr107
- csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f
- csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117
- csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f
- csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
- csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f
- csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137
- csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f
- sscratch sepc scause stval sip csr145 csr146 csr147
- csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f
- csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157
- csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f
- csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
- csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f
- csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177
- csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f
- satp csr181 csr182 csr183 csr184 csr185 csr186 csr187
- csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f
- csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197
- csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f
- csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7
- csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af
- csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7
- csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf
- csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7
- csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf
- csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7
- csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df
- csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7
- csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef
- csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7
- csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff
- vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207
- csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f
- csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217
- csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f
- csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227
- csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f
- csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237
- csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f
- vsscratch vsepc vscause vstval vsip csr245 csr246 csr247
- csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f
- csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257
- csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f
- csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267
- csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f
- csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277
- csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f
- vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287
- csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f
- csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297
- csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f
- csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7
- csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af
- csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7
- csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf
- csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7
- csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf
- csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7
- csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df
- csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7
- csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef
- csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7
- csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff
- mstatus misa medeleg mideleg mie mtvec mcounteren csr307
- csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f
- mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317
- csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f
- mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7
- mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
- mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23
- mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
- mscratch mepc mcause mtval mip csr345 csr346 csr347
- csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f
- csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357
- csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f
- csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367
- csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f
- csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377
- csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f
- mbase mbound mibase mibound mdbase mdbound csr386 csr387
- csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f
- csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397
- csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f
- pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7
- pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15
- pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7
- pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
- pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23
- pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31
- pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39
- pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47
- pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55
- pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63
- csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7
- csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff
- csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407
- csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f
- csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417
- csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f
- csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427
- csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f
- csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437
- csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f
- csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447
- csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f
- csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457
- csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f
- csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467
- csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f
- csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477
- csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f
- csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487
- csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f
- csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497
- csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f
- csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7
- csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af
- csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7
- csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf
- csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7
- csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf
- csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7
- csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df
- csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7
- csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef
- csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7
- csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff
- csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507
- csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f
- csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517
- csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f
- csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527
- csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f
- csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537
- csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f
- csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547
- csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f
- csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557
- csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f
- csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567
- csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f
- csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577
- csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f
- csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587
- csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f
- csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597
- csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f
- csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7
- scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af
- csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7
- csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf
- csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7
- csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf
- csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7
- csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df
- csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7
- csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef
- csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7
- csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff
- hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie
- csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f
- csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617
- csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f
- csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627
- csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f
- csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637
- csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f
- csr640 csr641 csr642 htval  hip    hvip   csr646 csr647
- csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f
- csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657
- csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f
- csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667
- csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f
- csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677
- csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f
- hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687
- csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f
- csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697
- csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f
- csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7
- hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af
- csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7
- csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf
- csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7
- csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf
- csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7
- csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df
- csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7
- csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef
- csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7
- csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff
- csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707
- csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f
- csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717
- csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f
- csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727
- csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f
- csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737
- csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f
- csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747
- csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f
- csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757
- csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f
- csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767
- csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f
- csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777
- csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f
- csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787
- csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f
- csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797
- csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f
- tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7
- mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af
- dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7
- csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf
- csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7
- csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf
- csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7
- csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df
- csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7
- csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef
- csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7
- csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff
- csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807
- csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f
- csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817
- csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f
- csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827
- csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f
- csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837
- csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f
- csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847
- csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f
- csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857
- csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f
- csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867
- csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f
- csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877
- csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f
- csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887
- csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f
- csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897
- csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f
- csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7
- csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af
- csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7
- csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf
- csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7
- csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf
- csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7
- csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df
- csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7
- csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef
- csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7
- csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff
- csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907
- csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f
- csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917
- csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f
- csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927
- csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f
- csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937
- csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f
- csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947
- csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f
- csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957
- csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f
- csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967
- csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f
- csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977
- csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f
- csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987
- csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f
- csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997
- csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f
- csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7
- csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af
- csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7
- csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf
- csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7
- csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf
- csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7
- csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df
- csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7
- csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef
- csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7
- csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff
- csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07
- csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f
- csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17
- csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f
- csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27
- csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f
- csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37
- csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f
- csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47
- csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f
- csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57
- csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f
- csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67
- csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f
- csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77
- csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f
- csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87
- csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f
- csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97
- csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f
- csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7
- csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf
- csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7
- csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf
- csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7
- csrac8 csrac9 csraca csracb csracc csracd csrace csracf
- csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7
- csrad8 csrad9 csrada csradb csradc csradd csrade csradf
- csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7
- csrae8 csrae9 csraea csraeb csraec csraed csraee csraef
- csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7
- csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff
- mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7
- mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
- mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23
- mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
- csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27
- csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f
- csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37
- csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f
- csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47
- csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f
- csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57
- csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f
- csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67
- csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f
- csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77
- csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f
- mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h
- mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h
- mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h
- mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h
- csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7
- csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf
- csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7
- csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf
- csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7
- csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf
- csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7
- csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf
- csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7
- csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef
- csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7
- csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff
- cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7
- hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
- hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23
- hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
- vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27
- csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f
- csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37
- csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f
- csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47
- csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f
- csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57
- csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f
- csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67
- csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f
- csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77
- csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f
- cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h
- hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
- hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h
- hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
- csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7
- csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf
- csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7
- csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf
- csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7
- csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf
- csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7
- csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf
- csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7
- csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef
- csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7
- csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff
- csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07
- csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f
- csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17
- csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f
- csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27
- csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f
- csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37
- csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f
- csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47
- csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f
- csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57
- csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f
- csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67
- csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f
- csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77
- csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f
- csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87
- csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f
- csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97
- csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f
- csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7
- csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf
- csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7
- csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf
- csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7
- csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf
- csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7
- csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf
- csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7
- csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef
- csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7
- csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff
- csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07
- csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f
- csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17
- csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f
- csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27
- csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f
- csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37
- csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f
- csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47
- csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f
- csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57
- csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f
- csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67
- csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f
- csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77
- csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f
- csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87
- csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f
- csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97
- csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f
- csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7
- csrea8 csrea9 csreaa csreab csreac csread csreae csreaf
- csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7
- csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf
- csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7
- csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf
- csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7
- csred8 csred9 csreda csredb csredc csredd csrede csredf
- csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7
- csree8 csree9 csreea csreeb csreec csreed csreee csreef
- csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7
- csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff
- csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07
- csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f
- csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17
- csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f
- csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27
- csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f
- csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37
- csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f
- csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47
- csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f
- csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57
- csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f
- csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67
- csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f
- csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77
- csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f
- csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87
- csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f
- csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97
- csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f
- csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7
- csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf
- csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7
- csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf
- csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7
- csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf
- csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7
- csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf
- csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7
- csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef
- csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7
- csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff
-];
-
-
-# SEE 3.1.1  Machine ISA Register  misa
+  
+  # SEE 3.1.1  Machine ISA Register  misa
 # (MXLEN-1, MXLEN-2) MXL - Machine XLEN  {1: 32, 2: 64, 3: 128}
 # Bit Character Description
 # 0   A         Atomic extension
@@ -603,34 +91,1056 @@ define register offset=0x90000000 size=$(XLEN) [
 # 23  X         Non-standard extensions present
 # 24  Y         Reserved
 # 25  Z         Reserved
-define context misa
-  RVA=(0,0)
-  RVB=(1,1)
-  RVC=(2,2)
-  RVD=(3,3)
-  RVE=(4,4)
-  RVF=(5,5)
-  RVG=(6,6)
-  RVH=(7,7)
-  RVI=(8,8)
-  RVJ=(9,9)
-  RVK=(10,10)
-  RVL=(11,11)
-  RVM=(12,12)
-  RVN=(13,13)
-  RVO=(14,14)
-  RVP=(15,15)
-  RVQ=(16,16)
-  RVR=(17,17)
-  RVS=(18,18)
-  RVT=(19,19)
-  RVU=(20,20)
-  RVV=(21,21)
-  RVW=(22,22)
-  RVX=(23,23)
-  RVY=(24,24)
-  RVZ=(25,25)
-  MXL=($(MXLEN_2), $(MXLEN_1))
+
+
+# Moved most CSR registers to .pspec file.  Doing so will:
+#  - Allow new registers to be named in the .pspec file
+#  - Processor variants differing only in CSR registers can just use a variant.pspec
+#  - Read/Write references to registers not defined in sleigh
+#  - Registers defined here will not get references to them
+#  - Allow rename and comment by end user
+
+#
+#  Control registers reserved 0x0000-0x0fff
+@define CSR_REG_START "0x0000"
+
+## CSR definitions is done as a big table with undefined holes so that
+## the 32-bit and 64-bit tables can be defined with the same code.
+## Otherwise the byte offset of the address of each register
+## would need to be calculated and would be different for XLEN of 32 or 64 bit.
+define csreg offset=$(CSR_REG_START) size=$(XLEN) [
+# 0x000
+ _       fflags frm     fcsr     _       _       _       _      
+# 0x008
+ _       _       _       _       _       _       _       _      
+# 0x010
+ _       _       _       _       _       _       _       _      
+# 0x018
+ _       _       _       _       _       _       _       _      
+# 0x020
+ _       _       _       _       _       _       _       _      
+# 0x028
+ _       _       _       _       _       _       _       _      
+# 0x030
+ _       _       _       _       _       _       _       _      
+# 0x038
+ _       _       _       _       _       _       _       _      
+# 0x040
+ _       uepc    _       _       _       _       _       _      
+# 0x048
+ _       _       _       _       _       _       _       _      
+# 0x050
+ _       _       _       _       _       _       _       _      
+# 0x058
+ _       _       _       _       _       _       _       _      
+# 0x060
+ _       _       _       _       _       _       _       _      
+# 0x068
+ _       _       _       _       _       _       _       _      
+# 0x070
+ _       _       _       _       _       _       _       _      
+# 0x078
+ _       _       _       _       _       _       _       _      
+# 0x080
+ _       _       _       _       _       _       _       _      
+# 0x088
+ _       _       _       _       _       _       _       _      
+# 0x090
+ _       _       _       _       _       _       _       _      
+# 0x098
+ _       _       _       _       _       _       _       _      
+# 0x0a0
+ _       _       _       _       _       _       _       _      
+# 0x0a8
+ _       _       _       _       _       _       _       _      
+# 0x0b0
+ _       _       _       _       _       _       _       _      
+# 0x0b8
+ _       _       _       _       _       _       _       _      
+# 0x0c0
+ _       _       _       _       _       _       _       _      
+# 0x0c8
+ _       _       _       _       _       _       _       _      
+# 0x0d0
+ _       _       _       _       _       _       _       _      
+# 0x0d8
+ _       _       _       _       _       _       _       _      
+# 0x0e0
+ _       _       _       _       _       _       _       _      
+# 0x0e8
+ _       _       _       _       _       _       _       _      
+# 0x0f0
+ _       _       _       _       _       _       _       _      
+# 0x0f8
+ _       _       _       _       _       _       _       _      
+# 0x100
+ _       _       _       _       _       _       _       _      
+# 0x108
+ _       _       _       _       _       _       _       _      
+# 0x110
+ _       _       _       _       _       _       _       _      
+# 0x118
+ _       _       _       _       _       _       _       _      
+# 0x120
+ _       _       _       _       _       _       _       _      
+# 0x128
+ _       _       _       _       _       _       _       _      
+# 0x130
+ _       _       _       _       _       _       _       _      
+# 0x138
+ _       _       _       _       _       _       _       _      
+# 0x140
+ _       sepc    _       _       _       _       _       _      
+# 0x148
+ _       _       _       _       _       _       _       _      
+# 0x150
+ _       _       _       _       _       _       _       _      
+# 0x158
+ _       _       _       _       _       _       _       _      
+# 0x160
+ _       _       _       _       _       _       _       _      
+# 0x168
+ _       _       _       _       _       _       _       _      
+# 0x170
+ _       _       _       _       _       _       _       _      
+# 0x178
+ _       _       _       _       _       _       _       _  
+# 0x180    
+ _       _       _       _       _       _       _       _      
+# 0x188
+ _       _       _       _       _       _       _       _      
+# 0x190
+ _       _       _       _       _       _       _       _      
+# 0x198
+ _       _       _       _       _       _       _       _      
+# 0x1a0
+ _       _       _       _       _       _       _       _      
+# 0x1a8
+ _       _       _       _       _       _       _       _      
+# 0x1b0
+ _       _       _       _       _       _       _       _      
+# 0x1b8
+ _       _       _       _       _       _       _       _      
+# 0x1c0
+ _       _       _       _       _       _       _       _      
+# 0x1c8
+ _       _       _       _       _       _       _       _      
+# 0x1d0
+ _       _       _       _       _       _       _       _      
+# 0x1d8
+ _       _       _       _       _       _       _       _      
+# 0x1e0
+ _       _       _       _       _       _       _       _      
+# 0x1e8
+ _       _       _       _       _       _       _       _      
+# 0x1f0
+ _       _       _       _       _       _       _       _      
+# 0x1f8
+ _       _       _       _       _       _       _       _      
+# 0x200
+ _       _       _       _       _       _       _       _      
+# 0x208
+ _       _       _       _       _       _       _       _      
+# 0x210
+ _       _       _       _       _       _       _       _      
+# 0x218
+ _       _       _       _       _       _       _       _      
+# 0x220
+ _       _       _       _       _       _       _       _      
+# 0x228
+ _       _       _       _       _       _       _       _      
+# 0x230
+ _       _       _       _       _       _       _       _      
+# 0x238
+ _       _       _       _       _       _       _       _    
+# 0x240  
+ _       _       _       _       _       _       _       _      
+# 0x248
+ _       _       _       _       _       _       _       _      
+# 0x250
+ _       _       _       _       _       _       _       _      
+# 0x258
+ _       _       _       _       _       _       _       _      
+# 0x260
+ _       _       _       _       _       _       _       _      
+# 0x268
+ _       _       _       _       _       _       _       _      
+# 0x270
+ _       _       _       _       _       _       _       _      
+# 0x278
+ _       _       _       _       _       _       _       _    
+# 0x280
+ _       _       _       _       _       _       _       _      
+# 0x288
+ _       _       _       _       _       _       _       _      
+# 0x290
+ _       _       _       _       _       _       _       _      
+# 0x298
+ _       _       _       _       _       _       _       _      
+# 0x2a0
+ _       _       _       _       _       _       _       _      
+# 0x2a8
+ _       _       _       _       _       _       _       _      
+# 0x2b0
+ _       _       _       _       _       _       _       _      
+# 0x2b8
+ _       _       _       _       _       _       _       _      
+# 0x2c0
+ _       _       _       _       _       _       _       _      
+# 0x2c8
+ _       _       _       _       _       _       _       _      
+# 0x2d0
+ _       _       _       _       _       _       _       _      
+# 0x2d8
+ _       _       _       _       _       _       _       _      
+# 0x2e0
+ _       _       _       _       _       _       _       _      
+# 0x2e8
+ _       _       _       _       _       _       _       _      
+# 0x2f0
+ _       _       _       _       _       _       _       _      
+# 0x2f8
+ _       _       _       _       _       _       _       _   
+# 0x310   
+ _       _       _       _       _       _       _       _      
+# 0x308
+ _       _       _       _       _       _       _       _    
+# 0x310  
+ _       _       _       _       _       _       _       _      
+# 0x318
+ _       _       _       _       _       _       _       _      
+# 0x320
+ _       _       _       _       _       _       _       _      
+# 0x328
+ _       _       _       _       _       _       _       _      
+# 0x330
+ _       _       _       _       _       _       _       _      
+# 0x338
+ _       _       _       _       _       _       _       _      
+# 0x318
+ _       mepc       _       _       _       _       _       _          
+# 0x348
+ _       _       _       _       _       _       _       _      
+# 0x350
+ _       _       _       _       _       _       _       _      
+# 0x358
+ _       _       _       _       _       _       _       _      
+# 0x360
+ _       _       _       _       _       _       _       _      
+# 0x368
+ _       _       _       _       _       _       _       _      
+# 0x370
+ _       _       _       _       _       _       _       _      
+# 0x378
+ _       _       _       _       _       _       _       _      
+# 0x380
+ _       _       _       _       _       _       _       _      
+# 0x388
+ _       _       _       _       _       _       _       _      
+# 0x390
+ _       _       _       _       _       _       _       _      
+# 0x398
+ _       _       _       _       _       _       _       _      
+# 0x3a0
+ _       _       _       _       _       _       _       _      
+# 0x3a8
+ _       _       _       _       _       _       _       _      
+# 0x3b0
+ _       _       _       _       _       _       _       _      
+# 0x3b8
+ _       _       _       _       _       _       _       _      
+# 0x3c0
+ _       _       _       _       _       _       _       _      
+# 0x3c8
+ _       _       _       _       _       _       _       _      
+# 0x3d0
+ _       _       _       _       _       _       _       _      
+# 0x3d8
+ _       _       _       _       _       _       _       _      
+# 0x3e0
+ _       _       _       _       _       _       _       _      
+# 0x3e8
+ _       _       _       _       _       _       _       _      
+# 0x3f0
+ _       _       _       _       _       _       _       _      
+# 0x3f8
+ _       _       _       _       _       _       _       _      
+# 0x400
+ _       _       _       _       _       _       _       _      
+# 0x408
+ _       _       _       _       _       _       _       _      
+# 0x410
+ _       _       _       _       _       _       _       _      
+# 0x418
+ _       _       _       _       _       _       _       _      
+# 0x420
+ _       _       _       _       _       _       _       _      
+# 0x428
+ _       _       _       _       _       _       _       _      
+# 0x430
+ _       _       _       _       _       _       _       _      
+# 0x438
+ _       _       _       _       _       _       _       _      
+# 0x440
+ _       _       _       _       _       _       _       _      
+# 0x448
+ _       _       _       _       _       _       _       _      
+# 0x450
+ _       _       _       _       _       _       _       _      
+# 0x458
+ _       _       _       _       _       _       _       _      
+# 0x460
+ _       _       _       _       _       _       _       _      
+# 0x468
+ _       _       _       _       _       _       _       _      
+# 0x470
+ _       _       _       _       _       _       _       _      
+# 0x478
+ _       _       _       _       _       _       _       _      
+# 0x480
+ _       _       _       _       _       _       _       _      
+# 0x488
+ _       _       _       _       _       _       _       _      
+# 0x490
+ _       _       _       _       _       _       _       _      
+# 0x498
+ _       _       _       _       _       _       _       _      
+# 0x4a0
+ _       _       _       _       _       _       _       _      
+# 0x4a8
+ _       _       _       _       _       _       _       _      
+# 0x4b0
+ _       _       _       _       _       _       _       _      
+# 0x4b8
+ _       _       _       _       _       _       _       _      
+# 0x4c0
+ _       _       _       _       _       _       _       _      
+# 0x4c8
+ _       _       _       _       _       _       _       _      
+# 0x4d0
+ _       _       _       _       _       _       _       _      
+# 0x4d8
+ _       _       _       _       _       _       _       _      
+# 0x4e0
+ _       _       _       _       _       _       _       _      
+# 0x4e8
+ _       _       _       _       _       _       _       _      
+# 0x4f0
+ _       _       _       _       _       _       _       _      
+# 0x4f8
+ _       _       _       _       _       _       _       _      
+# 0x500
+ _       _       _       _       _       _       _       _      
+# 0x508
+ _       _       _       _       _       _       _       _      
+# 0x510
+ _       _       _       _       _       _       _       _      
+# 0x518
+ _       _       _       _       _       _       _       _      
+# 0x520
+ _       _       _       _       _       _       _       _      
+# 0x528
+ _       _       _       _       _       _       _       _      
+# 0x530
+ _       _       _       _       _       _       _       _      
+# 0x538
+ _       _       _       _       _       _       _       _      
+# 0x540
+ _       _       _       _       _       _       _       _      
+# 0x548
+ _       _       _       _       _       _       _       _      
+# 0x550
+ _       _       _       _       _       _       _       _      
+# 0x558
+ _       _       _       _       _       _       _       _      
+# 0x560
+ _       _       _       _       _       _       _       _      
+# 0x568
+ _       _       _       _       _       _       _       _      
+# 0x570
+ _       _       _       _       _       _       _       _      
+# 0x578
+ _       _       _       _       _       _       _       _      
+# 0x580
+ _       _       _       _       _       _       _       _      
+# 0x588
+ _       _       _       _       _       _       _       _      
+# 0x590
+ _       _       _       _       _       _       _       _      
+# 0x598
+ _       _       _       _       _       _       _       _      
+# 0x5a0
+ _       _       _       _       _       _       _       _ 
+# 0x5a8     
+ _       _       _       _       _       _       _       _      
+# 0x5b0
+ _       _       _       _       _       _       _       _      
+# 0x5b8
+ _       _       _       _       _       _       _       _      
+# 0x5c0
+ _       _       _       _       _       _       _       _      
+# 0x5c8
+ _       _       _       _       _       _       _       _      
+# 0x5d0
+ _       _       _       _       _       _       _       _      
+# 0x5d8
+ _       _       _       _       _       _       _       _      
+# 0x5e0
+ _       _       _       _       _       _       _       _      
+# 0x5e8
+ _       _       _       _       _       _       _       _      
+# 0x5f0
+ _       _       _       _       _       _       _       _      
+# 0x5f8
+ _       _       _       _       _       _       _       _     
+# 0x600 
+ _       _       _       _       _       _       _       _      
+# 0x608
+ _       _       _       _       _       _       _       _      
+# 0x610
+ _       _       _       _       _       _       _       _      
+# 0x618
+ _       _       _       _       _       _       _       _      
+# 0x620
+ _       _       _       _       _       _       _       _      
+# 0x628
+ _       _       _       _       _       _       _       _      
+# 0x630
+ _       _       _       _       _       _       _       _      
+# 0x638
+ _       _       _       _       _       _       _       _      
+# 0x640
+ _       _       _       _       _       _       _       _      
+# 0x648
+ _       _       _       _       _       _       _       _      
+# 0x650
+ _       _       _       _       _       _       _       _      
+# 0x658
+ _       _       _       _       _       _       _       _      
+# 0x660
+ _       _       _       _       _       _       _       _      
+# 0x668
+ _       _       _       _       _       _       _       _      
+# 0x670
+ _       _       _       _       _       _       _       _      
+# 0x678
+ _       _       _       _       _       _       _       _     
+# 0x680 
+ _       _       _       _       _       _       _       _      
+# 0x688
+ _       _       _       _       _       _       _       _      
+# 0x690
+ _       _       _       _       _       _       _       _      
+# 0x698
+ _       _       _       _       _       _       _       _      
+# 0x6a0
+ _       _       _       _       _       _       _       _   
+# 0x6a8   
+ _       _       _       _       _       _       _       _      
+# 0x6b0
+ _       _       _       _       _       _       _       _      
+# 0x6b8
+ _       _       _       _       _       _       _       _      
+# 0x6c0
+ _       _       _       _       _       _       _       _      
+# 0x6c8
+ _       _       _       _       _       _       _       _      
+# 0x6d0
+ _       _       _       _       _       _       _       _      
+# 0x6d8
+ _       _       _       _       _       _       _       _      
+# 0x6e0
+ _       _       _       _       _       _       _       _      
+# 0x6e8
+ _       _       _       _       _       _       _       _      
+# 0x6f0
+ _       _       _       _       _       _       _       _      
+# 0x6f8
+ _       _       _       _       _       _       _       _      
+# 0x700
+ _       _       _       _       _       _       _       _      
+# 0x708
+ _       _       _       _       _       _       _       _      
+# 0x710
+ _       _       _       _       _       _       _       _      
+# 0x718
+ _       _       _       _       _       _       _       _      
+# 0x720
+ _       _       _       _       _       _       _       _      
+# 0x728
+ _       _       _       _       _       _       _       _      
+# 0x730
+ _       _       _       _       _       _       _       _      
+# 0x738
+ _       _       _       _       _       _       _       _      
+# 0x740
+ _       _       _       _       _       _       _       _      
+# 0x748
+ _       _       _       _       _       _       _       _      
+# 0x750
+ _       _       _       _       _       _       _       _      
+# 0x758
+ _       _       _       _       _       _       _       _      
+# 0x760
+ _       _       _       _       _       _       _       _      
+# 0x768
+ _       _       _       _       _       _       _       _      
+# 0x770
+ _       _       _       _       _       _       _       _      
+# 0x778
+ _       _       _       _       _       _       _       _      
+# 0x780
+ _       _       _       _       _       _       _       _      
+# 0x788
+ _       _       _       _       _       _       _       _      
+# 0x790
+ _       _       _       _       _       _       _       _      
+# 0x798
+ _       _       _       _       _       _       _       _     
+# 0x7a0
+ _       _       _       _       _       _       _       _      
+# 0x7a8
+ _       _       _       _       _       _       _       _      
+# 0x7b0
+ dcsr dpc dscratch0 dscratch1 _       _       _       _      
+# 0x7b8
+ _       _       _       _       _       _       _       _      
+# 0x7c0
+ _       _       _       _       _       _       _       _      
+# 0x7c8
+ _       _       _       _       _       _       _       _      
+# 0x7d0
+ _       _       _       _       _       _       _       _      
+# 0x7d8
+ _       _       _       _       _       _       _       _      
+# 0x7e0
+ _       _       _       _       _       _       _       _      
+# 0x7e8
+ _       _       _       _       _       _       _       _      
+# 0x7f0
+ _       _       _       _       _       _       _       _      
+# 0x7f8
+ _       _       _       _       _       _       _       _      
+# 0x800
+ _       _       _       _       _       _       _       _      
+# 0x808
+ _       _       _       _       _       _       _       _      
+# 0x810
+ _       _       _       _       _       _       _       _      
+# 0x818
+ _       _       _       _       _       _       _       _      
+# 0x820
+ _       _       _       _       _       _       _       _      
+# 0x828
+ _       _       _       _       _       _       _       _      
+# 0x830
+ _       _       _       _       _       _       _       _      
+# 0x838
+ _       _       _       _       _       _       _       _      
+# 0x840
+ _       _       _       _       _       _       _       _      
+# 0x848
+ _       _       _       _       _       _       _       _      
+# 0x850
+ _       _       _       _       _       _       _       _      
+# 0x858
+ _       _       _       _       _       _       _       _      
+# 0x860
+ _       _       _       _       _       _       _       _      
+# 0x868
+ _       _       _       _       _       _       _       _      
+# 0x870
+ _       _       _       _       _       _       _       _      
+# 0x878
+ _       _       _       _       _       _       _       _      
+# 0x880
+ _       _       _       _       _       _       _       _      
+# 0x888
+ _       _       _       _       _       _       _       _      
+# 0x890
+ _       _       _       _       _       _       _       _      
+# 0x898
+ _       _       _       _       _       _       _       _      
+# 0x8a0
+ _       _       _       _       _       _       _       _      
+# 0x8a8
+ _       _       _       _       _       _       _       _      
+# 0x8b0
+ _       _       _       _       _       _       _       _      
+# 0x8b8
+ _       _       _       _       _       _       _       _      
+# 0x8c0
+ _       _       _       _       _       _       _       _      
+# 0x8c8
+ _       _       _       _       _       _       _       _      
+# 0x8d0
+ _       _       _       _       _       _       _       _      
+# 0x8d8
+ _       _       _       _       _       _       _       _      
+# 0x8e0
+ _       _       _       _       _       _       _       _      
+# 0x8e8
+ _       _       _       _       _       _       _       _      
+# 0x8f0
+ _       _       _       _       _       _       _       _      
+# 0x8f8
+ _       _       _       _       _       _       _       _      
+# 0x900
+ _       _       _       _       _       _       _       _      
+# 0x908
+ _       _       _       _       _       _       _       _      
+# 0x910
+ _       _       _       _       _       _       _       _      
+# 0x918
+ _       _       _       _       _       _       _       _      
+# 0x920
+ _       _       _       _       _       _       _       _      
+# 0x928
+ _       _       _       _       _       _       _       _      
+# 0x930
+ _       _       _       _       _       _       _       _      
+# 0x938
+ _       _       _       _       _       _       _       _      
+# 0x940
+ _       _       _       _       _       _       _       _      
+# 0x948
+ _       _       _       _       _       _       _       _      
+# 0x950
+ _       _       _       _       _       _       _       _      
+# 0x958
+ _       _       _       _       _       _       _       _      
+# 0x960
+ _       _       _       _       _       _       _       _      
+# 0x968
+ _       _       _       _       _       _       _       _      
+# 0x970
+ _       _       _       _       _       _       _       _      
+# 0x978
+ _       _       _       _       _       _       _       _      
+# 0x980
+ _       _       _       _       _       _       _       _      
+# 0x988
+ _       _       _       _       _       _       _       _      
+# 0x990
+ _       _       _       _       _       _       _       _      
+# 0x998
+ _       _       _       _       _       _       _       _      
+# 0x9a0
+ _       _       _       _       _       _       _       _      
+# 0x9a8
+ _       _       _       _       _       _       _       _      
+# 0x9b0
+ _       _       _       _       _       _       _       _      
+# 0x9b8
+ _       _       _       _       _       _       _       _      
+# 0x9c0
+ _       _       _       _       _       _       _       _      
+# 0x9c8
+ _       _       _       _       _       _       _       _      
+# 0x9d0
+ _       _       _       _       _       _       _       _      
+# 0x9d8
+ _       _       _       _       _       _       _       _      
+# 0x9e0
+ _       _       _       _       _       _       _       _      
+# 0x9e8
+ _       _       _       _       _       _       _       _      
+# 0x9f0
+ _       _       _       _       _       _       _       _      
+# 0x9f8
+ _       _       _       _       _       _       _       _      
+# 0xa00
+ _       _       _       _       _       _       _       _      
+# 0xa08
+ _       _       _       _       _       _       _       _      
+# 0xa10
+ _       _       _       _       _       _       _       _      
+# 0xa18
+ _       _       _       _       _       _       _       _      
+# 0xa20
+ _       _       _       _       _       _       _       _      
+# 0xa28
+ _       _       _       _       _       _       _       _      
+# 0xa30
+ _       _       _       _       _       _       _       _      
+# 0xa38
+ _       _       _       _       _       _       _       _      
+# 0xa40
+ _       _       _       _       _       _       _       _      
+# 0xa48
+ _       _       _       _       _       _       _       _      
+# 0xa50
+ _       _       _       _       _       _       _       _      
+# 0xa58
+ _       _       _       _       _       _       _       _      
+# 0xa60
+ _       _       _       _       _       _       _       _      
+# 0xa68
+ _       _       _       _       _       _       _       _      
+# 0xa70
+ _       _       _       _       _       _       _       _      
+# 0xa78
+ _       _       _       _       _       _       _       _      
+# 0xa80
+ _       _       _       _       _       _       _       _      
+# 0xa88
+ _       _       _       _       _       _       _       _      
+# 0xa90
+ _       _       _       _       _       _       _       _      
+# 0xa98
+ _       _       _       _       _       _       _       _      
+# 0xaa0
+ _       _       _       _       _       _       _       _      
+# 0xaa8
+ _       _       _       _       _       _       _       _      
+# 0xab0
+ _       _       _       _       _       _       _       _      
+# 0xab8
+ _       _       _       _       _       _       _       _      
+# 0xac0
+ _       _       _       _       _       _       _       _      
+# 0xac8
+ _       _       _       _       _       _       _       _      
+# 0xad0
+ _       _       _       _       _       _       _       _      
+# 0xad8
+ _       _       _       _       _       _       _       _      
+# 0xae0
+ _       _       _       _       _       _       _       _      
+# 0xae8
+ _       _       _       _       _       _       _       _      
+# 0xaf0
+ _       _       _       _       _       _       _       _      
+# 0xaf8
+ _       _       _       _       _       _       _       _      
+# 0xa00
+ _       _       _       _       _       _       _       _      
+# 0xa08
+ _       _       _       _       _       _       _       _      
+# 0xa10
+ _       _       _       _       _       _       _       _      
+# 0xa18
+ _       _       _       _       _       _       _       _      
+# 0xb20
+ _       _       _       _       _       _       _       _      
+# 0xb28
+ _       _       _       _       _       _       _       _      
+# 0xb30
+ _       _       _       _       _       _       _       _      
+# 0xb38
+ _       _       _       _       _       _       _       _      
+# 0xb40
+ _       _       _       _       _       _       _       _      
+# 0xb48
+ _       _       _       _       _       _       _       _      
+# 0xb50
+ _       _       _       _       _       _       _       _      
+# 0xb58
+ _       _       _       _       _       _       _       _      
+# 0xb60
+ _       _       _       _       _       _       _       _      
+# 0xb68
+ _       _       _       _       _       _       _       _      
+# 0xb70
+ _       _       _       _       _       _       _       _      
+# 0xb78
+ _       _       _       _       _       _       _       _      
+# 0xb80
+ _       _       _       _       _       _       _       _      
+# 0xb88
+ _       _       _       _       _       _       _       _      
+# 0xb90
+ _       _       _       _       _       _       _       _      
+# 0xb98
+ _       _       _       _       _       _       _       _      
+# 0xba0
+ _       _       _       _       _       _       _       _      
+# 0xba8
+ _       _       _       _       _       _       _       _      
+# 0xbb0
+ _       _       _       _       _       _       _       _      
+# 0xbb8
+ _       _       _       _       _       _       _       _      
+# 0xbc0
+ _       _       _       _       _       _       _       _      
+# 0xbc8
+ _       _       _       _       _       _       _       _      
+# 0xbd0
+ _       _       _       _       _       _       _       _      
+# 0xbd8
+ _       _       _       _       _       _       _       _      
+# 0xbe0
+ _       _       _       _       _       _       _       _      
+# 0xbe8
+ _       _       _       _       _       _       _       _      
+# 0xbf0
+ _       _       _       _       _       _       _       _      
+# 0xbf8
+ _       _       _       _       _       _       _       _      
+# 0xc00
+ _       _       _       _       _       _       _       _
+# 0xc08
+ _       _       _       _       _       _       _       _
+# 0xc10
+ _       _       _       _       _       _       _       _
+# 0xc18
+ _       _       _       _       _       _       _       _
+# 0xc20
+ _       _       _       _       _       _       _       _
+# 0xc28
+ _       _       _       _       _       _       _       _      
+# 0xc30
+ _       _       _       _       _       _       _       _      
+# 0xc38
+ _       _       _       _       _       _       _       _      
+# 0xc40
+ _       _       _       _       _       _       _       _      
+# 0xc48
+ _       _       _       _       _       _       _       _      
+# 0xc50
+ _       _       _       _       _       _       _       _      
+# 0xc58
+ _       _       _       _       _       _       _       _      
+# 0xc60
+ _       _       _       _       _       _       _       _      
+# 0xc68
+ _       _       _       _       _       _       _       _      
+# 0xc70
+ _       _       _       _       _       _       _       _      
+# 0xc78
+ _       _       _       _       _       _       _       _      
+# 0xc80
+ _       _       _       _       _       _       _       _      
+# 0xc88
+ _       _       _       _       _       _       _       _      
+# 0xc90
+ _       _       _       _       _       _       _       _      
+# 0xc98
+ _       _       _       _       _       _       _       _      
+# 0xca0
+ _       _       _       _       _       _       _       _      
+# 0xca8
+ _       _       _       _       _       _       _       _      
+# 0xcb0
+ _       _       _       _       _       _       _       _      
+# 0xcb8
+ _       _       _       _       _       _       _       _      
+# 0xcc0
+ _       _       _       _       _       _       _       _      
+# 0xcc8
+ _       _       _       _       _       _       _       _      
+# 0xcd0
+ _       _       _       _       _       _       _       _      
+# 0xcd8
+ _       _       _       _       _       _       _       _      
+# 0xce0
+ _       _       _       _       _       _       _       _      
+# 0xce8
+ _       _       _       _       _       _       _       _      
+# 0xcf0
+ _       _       _       _       _       _       _       _      
+# 0xcf8
+ _       _       _       _       _       _       _       _      
+# 0xd00
+ _       _       _       _       _       _       _       _      
+# 0xd08
+ _       _       _       _       _       _       _       _      
+# 0xd10
+ _       _       _       _       _       _       _       _      
+# 0xd18
+ _       _       _       _       _       _       _       _      
+# 0xd20
+ _       _       _       _       _       _       _       _      
+# 0xd28
+ _       _       _       _       _       _       _       _      
+# 0xd30
+ _       _       _       _       _       _       _       _      
+# 0xd38
+ _       _       _       _       _       _       _       _      
+# 0xd40
+ _       _       _       _       _       _       _       _      
+# 0xd48
+ _       _       _       _       _       _       _       _      
+# 0xd50
+ _       _       _       _       _       _       _       _      
+# 0xd58
+ _       _       _       _       _       _       _       _      
+# 0xd60
+ _       _       _       _       _       _       _       _      
+# 0xd68
+ _       _       _       _       _       _       _       _      
+# 0xd70
+ _       _       _       _       _       _       _       _      
+# 0xd78
+ _       _       _       _       _       _       _       _      
+# 0xd80
+ _       _       _       _       _       _       _       _      
+# 0xd88
+ _       _       _       _       _       _       _       _      
+# 0xd90
+ _       _       _       _       _       _       _       _      
+# 0xd98
+ _       _       _       _       _       _       _       _      
+# 0xda0
+ _       _       _       _       _       _       _       _      
+# 0xda8
+ _       _       _       _       _       _       _       _      
+# 0xdb0
+ _       _       _       _       _       _       _       _      
+# 0xdb8
+ _       _       _       _       _       _       _       _      
+# 0xdc0
+ _       _       _       _       _       _       _       _      
+# 0xdc8
+ _       _       _       _       _       _       _       _      
+# 0xdd0
+ _       _       _       _       _       _       _       _      
+# 0xdd8
+ _       _       _       _       _       _       _       _      
+# 0xde0
+ _       _       _       _       _       _       _       _      
+# 0xde8
+ _       _       _       _       _       _       _       _      
+# 0xdf0
+ _       _       _       _       _       _       _       _      
+# 0xdf8
+ _       _       _       _       _       _       _       _      
+# 0xe00
+ _       _       _       _       _       _       _       _      
+# 0xe08
+ _       _       _       _       _       _       _       _      
+# 0xe10
+ _       _       _       _       _       _       _       _      
+# 0xe18
+ _       _       _       _       _       _       _       _      
+# 0xe20
+ _       _       _       _       _       _       _       _      
+# 0xe28
+ _       _       _       _       _       _       _       _      
+# 0xe30
+ _       _       _       _       _       _       _       _      
+# 0xe38
+ _       _       _       _       _       _       _       _      
+# 0xe40
+ _       _       _       _       _       _       _       _      
+# 0xe48
+ _       _       _       _       _       _       _       _      
+# 0xe50
+ _       _       _       _       _       _       _       _      
+# 0xe58
+ _       _       _       _       _       _       _       _      
+# 0xe60
+ _       _       _       _       _       _       _       _      
+# 0xe68
+ _       _       _       _       _       _       _       _      
+# 0xe70
+ _       _       _       _       _       _       _       _      
+# 0xe78
+ _       _       _       _       _       _       _       _      
+# 0xe80
+ _       _       _       _       _       _       _       _      
+# 0xe88
+ _       _       _       _       _       _       _       _      
+# 0xe90
+ _       _       _       _       _       _       _       _      
+# 0xe98
+ _       _       _       _       _       _       _       _      
+# 0xea0
+ _       _       _       _       _       _       _       _      
+# 0xea8
+ _       _       _       _       _       _       _       _      
+# 0xeb0
+ _       _       _       _       _       _       _       _      
+# 0xeb8
+ _       _       _       _       _       _       _       _      
+# 0xec0
+ _       _       _       _       _       _       _       _      
+# 0xec8
+ _       _       _       _       _       _       _       _      
+# 0xed0
+ _       _       _       _       _       _       _       _      
+# 0xed8
+ _       _       _       _       _       _       _       _      
+# 0xee0
+ _       _       _       _       _       _       _       _      
+# 0xee8
+ _       _       _       _       _       _       _       _      
+# 0xef0
+ _       _       _       _       _       _       _       _      
+# 0xef8
+ _       _       _       _       _       _       _       _      
+# 0xf00
+ _       _       _       _       _       _       _       _      
+# 0xf08
+ _       _       _       _       _       _       _       _      
+# 0xf10
+ _       _       _       _       _       _       _       _      
+# 0xf18
+ _       _       _       _       _       _       _       _      
+# 0xf20
+ _       _       _       _       _       _       _       _      
+# 0xf28
+ _       _       _       _       _       _       _       _      
+# 0xf30
+ _       _       _       _       _       _       _       _      
+# 0xf38
+ _       _       _       _       _       _       _       _      
+# 0xf40
+ _       _       _       _       _       _       _       _      
+# 0xf48
+ _       _       _       _       _       _       _       _      
+# 0xf50
+ _       _       _       _       _       _       _       _      
+# 0xf58
+ _       _       _       _       _       _       _       _      
+# 0xf60
+ _       _       _       _       _       _       _       _      
+# 0xf68
+ _       _       _       _       _       _       _       _      
+# 0xf70
+ _       _       _       _       _       _       _       _      
+# 0xf78
+ _       _       _       _       _       _       _       _      
+# 0xf80
+ _       _       _       _       _       _       _       _      
+# 0xf88
+ _       _       _       _       _       _       _       _      
+# 0xf90
+ _       _       _       _       _       _       _       _      
+# 0xf98
+ _       _       _       _       _       _       _       _      
+# 0xfa0
+ _       _       _       _       _       _       _       _      
+# 0xfa8
+ _       _       _       _       _       _       _       _      
+# 0xfb0
+ _       _       _       _       _       _       _       _      
+# 0xfb8
+ _       _       _       _       _       _       _       _      
+# 0xfc0
+ _       _       _       _       _       _       _       _      
+# 0xfc8
+ _       _       _       _       _       _       _       _      
+# 0xfd0
+ _       _       _       _       _       _       _       _      
+# 0xfd8
+ _       _       _       _       _       _       _       _      
+# 0xfe0
+ _       _       _       _       _       _       _       _      
+# 0xfe8
+ _       _       _       _       _       _       _       _      
+# 0xff0
+ _       _       _       _       _       _       _       _      
+# 0xff8
+ _       _       _       _       _       _       _       _      
+];
+
+
+
+
+define context CONTEXT
+  reserved=(0,3)
+  MXL=(4,5)   # MXL - Machine XLEN  {1: 32, 2: 64, 3: 128}
 ;
 
 
@@ -644,12 +1154,19 @@ define token instr (32)
   r0711=(7,11)
   fr0711=(7,11)
   v0711=(7,11)
+  op0808=(8,8)
+  op0809=(8,9)
   op0811=(8,11)
+  op0911=(9,11)
+  op1011=(10,11)
+  op1213=(12,13)
   op1214=(12,14)
   funct3=(12,14)
   op1219=(12,19)
   op1231=(12,31)
   sop1231=(12,31) signed
+  op1414=(14,14)
+  op1516=(15,16)
   op1519=(15,19)
   sop1519=(15,19) signed
   subf5=(15,19)
@@ -658,6 +1175,7 @@ define token instr (32)
   v1519=(15,19)
   op1527=(15,27)
   op1531=(15,31)
+  op1719=(17,19)
   op2020=(20,20)
   op2022=(20,22)
   succ=(20,23)
@@ -710,10 +1228,12 @@ define token instr (32)
   op2031=(20,31)
   sop2031=(20,31) signed
   op2121=(21,21)
+  op2122=(21,22)
   op2130=(21,30)
   op2222=(22,22)
   op2323=(23,23)
   op2324=(23,24)
+  op2330=(23,30)
   op2424=(24,24)
   op2427=(24,27)
   pred=(24,27)
@@ -739,6 +1259,7 @@ define token instr (32)
   op2829=(28,29)
   fm=(28,31)
   op2931=(29,31)
+  op3030=(30,30)
   op3031=(30,31)
   op3131=(31,31)
   sop3131=(31,31) signed
@@ -774,6 +1295,7 @@ define token cinstr (16)
   cop0710=(7,10)
   cop0711=(7,11)
   cr0711=(7,11)
+  cd0711NoSp=(7,11)
   cd0711=(7,11)  
   cfr0711=(7,11)
   cop0712=(7,12)
@@ -792,582 +1314,3 @@ define token cinstr (16)
 ;
 
 
-attach variables [ r0711 r1519 r2024 r2731 ]
-       		 [ zero ra sp gp tp t0 t1 t2 s0 s1 a0  a1  a2 a3 a4 a5
-		   a6   a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
-
-attach variables [ cr0206 cr0711 cd0711 ]
-       		 [ zero ra sp gp tp t0 t1 t2 s0 s1 a0  a1  a2 a3 a4 a5
-		   a6   a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
-
-attach variables [ cr0204s cr0709s cd0709s ]
-       		 [ s0 s1 a0 a1 a2 a3 a4 a5 ];
-
-
-attach variables [ fr0711 fr1519 fr2024 fr2731 ]
-       		 [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0  fa1  fa2 fa3 fa4  fa5
-		   fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
-
-attach variables [ cfr0206 cfr0711 ]
-       		 [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0  fa1  fa2 fa3 fa4  fa5
-		   fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
-
-attach variables [ cfr0204s cfr0709s ]
-       		 [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ];
-
-
-attach variables [ v0711 v1519 v2024 ]
-       		 [ v0  v1  v2  v3  v4  v5  v6  v7  v8  v9  v10 v11 v12 v13 v14 v15
-		   v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];
-
-
-attach variables [ csr_0 ]
-                 [ ustatus fflags frm fcsr uie utvec csr006 csr007
-                   vstart vxsat  vxrm   csr00b csr00c csr00d csr00e vcsr
-                   csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017
-                   csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f
-                   csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027
-                   csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f
-                   csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037
-                   csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f
-                   uscratch uepc ucause utval uip csr045 csr046 csr047
-                   csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f
-                   csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057
-                   csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f
-                   csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067
-                   csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f
-                   csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077
-                   csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f
-                   csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087
-                   csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f
-                   csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097
-                   csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f
-                   csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7
-                   csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af
-                   csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7
-                   csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf
-                   csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7
-                   csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf
-                   csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7
-                   csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df
-                   csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7
-                   csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef
-                   csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7
-                   csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ];
-attach variables [ csr_1 ]
-                 [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107
-                   csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f
-                   csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117
-                   csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f
-                   csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
-                   csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f
-                   csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137
-                   csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f
-                   sscratch sepc scause stval sip csr145 csr146 csr147
-                   csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f
-                   csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157
-                   csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f
-                   csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
-                   csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f
-                   csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177
-                   csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f
-                   satp csr181 csr182 csr183 csr184 csr185 csr186 csr187
-                   csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f
-                   csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197
-                   csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f
-                   csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7
-                   csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af
-                   csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7
-                   csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf
-                   csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7
-                   csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf
-                   csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7
-                   csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df
-                   csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7
-                   csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef
-                   csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7
-                   csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ];
-attach variables [ csr_2 ]
-                 [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207
-                   csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f
-                   csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217
-                   csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f
-                   csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227
-                   csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f
-                   csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237
-                   csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f
-                   vsscratch vsepc vscause vstval vsip csr245 csr246 csr247
-                   csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f
-                   csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257
-                   csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f
-                   csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267
-                   csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f
-                   csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277
-                   csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f
-                   vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287
-                   csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f
-                   csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297
-                   csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f
-                   csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7
-                   csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af
-                   csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7
-                   csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf
-                   csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7
-                   csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf
-                   csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7
-                   csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df
-                   csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7
-                   csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef
-                   csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7
-                   csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ];
-attach variables [ csr_3 ]
-                 [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307
-                   csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f
-                   mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317
-                   csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f
-                   mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7
-                   mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
-                   mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23
-                   mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
-                   mscratch mepc mcause mtval mip csr345 csr346 csr347
-                   csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f
-                   csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357
-                   csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f
-                   csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367
-                   csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f
-                   csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377
-                   csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f
-                   mbase mbound mibase mibound mdbase mdbound csr386 csr387
-                   csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f
-                   csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397
-                   csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f
-                   pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7
-                   pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15
-                   pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7
-                   pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
-                   pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23
-                   pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31
-                   pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39
-                   pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47
-                   pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55
-                   pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63
-                   csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7
-                   csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ];
-attach variables [ csr_4 ]
-                 [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407
-                   csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f
-                   csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417
-                   csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f
-                   csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427
-                   csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f
-                   csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437
-                   csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f
-                   csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447
-                   csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f
-                   csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457
-                   csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f
-                   csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467
-                   csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f
-                   csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477
-                   csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f
-                   csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487
-                   csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f
-                   csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497
-                   csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f
-                   csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7
-                   csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af
-                   csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7
-                   csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf
-                   csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7
-                   csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf
-                   csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7
-                   csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df
-                   csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7
-                   csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef
-                   csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7
-                   csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ];
-attach variables [ csr_50 ]
-                 [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507
-                   csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f
-                   csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517
-                   csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f
-                   csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527
-                   csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f
-                   csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537
-                   csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f
-                   csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547
-                   csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f
-                   csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557
-                   csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f
-                   csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567
-                   csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f
-                   csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577
-                   csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ];
-attach variables [ csr_58 ]
-                 [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587
-                    csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f
-                    csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597
-                    csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f
-                    csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7
-                    scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af
-                    csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7
-                    csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ];
-attach variables [ csr_5C ]
-                 [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7
-                   csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf
-                   csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7
-                   csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df
-                   csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7
-                   csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef
-                   csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7
-                   csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ];
-attach variables [ csr_60 ]
-                 [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie
-                   csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f
-                   csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617
-                   csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f
-                   csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627
-                   csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f
-                   csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637
-                   csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f
-                   csr640 csr641 csr642 htval  hip    hvip   csr646 csr647
-                   csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f
-                   csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657
-                   csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f
-                   csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667
-                   csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f
-                   csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677
-                   csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ];
-attach variables [ csr_68 ]
-                 [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687
-                   csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f
-                   csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697
-                   csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f
-                   csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7
-                   hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af
-                   csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7
-                   csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ];
-attach variables [ csr_6C ]
-                 [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7
-                   csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf
-                   csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7
-                   csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df
-                   csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7
-                   csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef
-                   csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7
-                   csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ];
-attach variables [ csr_70 ]
-                 [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707
-                   csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f
-                   csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717
-                   csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f
-                   csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727
-                   csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f
-                   csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737
-                   csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f
-                   csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747
-                   csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f
-                   csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757
-                   csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f
-                   csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767
-                   csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f
-                   csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777
-                   csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ];
-attach variables [ csr_78 ]
-                 [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787
-                   csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f
-                   csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797
-                   csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ];
-attach variables [ csr_7A ]
-                 [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7
-                   mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ];
-attach variables [ csr_7B ]
-                 [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7
-                   csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ];
-attach variables [ csr_7C ]
-                 [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7
-                   csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf
-                   csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7
-                   csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df
-                   csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7
-                   csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef
-                   csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7
-                   csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ];
-attach variables [ csr_8 ]
-                 [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807
-                   csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f
-                   csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817
-                   csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f
-                   csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827
-                   csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f
-                   csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837
-                   csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f
-                   csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847
-                   csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f
-                   csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857
-                   csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f
-                   csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867
-                   csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f
-                   csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877
-                   csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f
-                   csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887
-                   csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f
-                   csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897
-                   csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f
-                   csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7
-                   csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af
-                   csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7
-                   csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf
-                   csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7
-                   csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf
-                   csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7
-                   csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df
-                   csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7
-                   csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef
-                   csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7
-                   csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ];
-attach variables [ csr_90 ]
-                 [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907
-                   csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f
-                   csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917
-                   csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f
-                   csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927
-                   csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f
-                   csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937
-                   csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f
-                   csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947
-                   csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f
-                   csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957
-                   csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f
-                   csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967
-                   csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f
-                   csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977
-                   csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ];
-attach variables [ csr_98 ]
-                 [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987
-                   csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f
-                   csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997
-                   csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f
-                   csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7
-                   csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af
-                   csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7
-                   csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ];
-attach variables [ csr_9C ]
-                 [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7
-                   csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf
-                   csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7
-                   csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df
-                   csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7
-                   csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef
-                   csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7
-                   csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ];
-attach variables [ csr_A0 ]
-                 [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07
-                   csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f
-                   csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17
-                   csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f
-                   csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27
-                   csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f
-                   csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37
-                   csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f
-                   csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47
-                   csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f
-                   csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57
-                   csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f
-                   csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67
-                   csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f
-                   csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77
-                   csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ];
-attach variables [ csr_A8 ]
-                 [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87
-                   csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f
-                   csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97
-                   csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f
-                   csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7
-                   csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf
-                   csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7
-                   csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ];
-attach variables [ csr_AC ]
-                 [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7
-                   csrac8 csrac9 csraca csracb csracc csracd csrace csracf
-                   csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7
-                   csrad8 csrad9 csrada csradb csradc csradd csrade csradf
-                   csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7
-                   csrae8 csrae9 csraea csraeb csraec csraed csraee csraef
-                   csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7
-                   csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ];
-attach variables [ csr_B0 ]
-                 [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7
-                   mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
-                   mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23
-                   mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
-                   csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27
-		   csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f
-		   csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37
-		   csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f
-                   csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47
-                   csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f
-                   csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57
-                   csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f
-                   csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67
-                   csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f
-                   csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77
-                   csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ];
-attach variables [ csr_B8 ]
-                 [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h
-                   mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h
-                   mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h
-                   mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h
-                   csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7
-                   csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf
-                   csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7
-                   csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ];
-attach variables [ csr_BC ]
-                 [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7
-                   csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf
-                   csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7
-                   csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf
-                   csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7
-                   csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef
-                   csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7
-                   csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ];
-attach variables [ csr_C0 ]
-                 [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7
-                   hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
-                   hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23
-                   hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
-                   vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27
-                   csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f
-                   csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37
-                   csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f
-                   csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47
-                   csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f
-                   csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57
-                   csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f
-                   csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67
-                   csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f
-                   csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77
-                   csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ];
-attach variables [ csr_C8 ]
-                 [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h
-                   hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
-                   hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h
-                   hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
-                   csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7
-                   csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf
-                   csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7
-                   csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ];
-attach variables [ csr_CC ]
-                 [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7
-                   csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf
-                   csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7
-                   csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf
-                   csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7
-                   csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef
-                   csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7
-                   csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ];
-attach variables [ csr_D0 ]
-                 [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07
-                   csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f
-                   csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17
-                   csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f
-                   csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27
-                   csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f
-                   csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37
-                   csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f
-                   csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47
-                   csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f
-                   csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57
-                   csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f
-                   csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67
-                   csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f
-                   csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77
-                   csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ];
-attach variables [ csr_D8 ]
-                 [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87
-                   csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f
-                   csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97
-                   csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f
-                   csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7
-                   csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf
-                   csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7
-                   csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ];
-attach variables [ csr_DC ]
-                 [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7
-                   csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf
-                   csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7
-                   csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf
-                   csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7
-                   csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef
-                   csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7
-                   csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ];
-attach variables [ csr_E0 ]
-                 [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07
-                   csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f
-                   csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17
-                   csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f
-                   csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27
-                   csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f
-                   csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37
-                   csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f
-                   csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47
-                   csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f
-                   csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57
-                   csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f
-                   csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67
-                   csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f
-                   csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77
-                   csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ];
-attach variables [ csr_E8 ]
-                 [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87
-                   csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f
-                   csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97
-                   csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f
-                   csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7
-                   csrea8 csrea9 csreaa csreab csreac csread csreae csreaf
-                   csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7
-                   csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ];
-attach variables [ csr_EC ]
-                 [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7
-                   csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf
-                   csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7
-                   csred8 csred9 csreda csredb csredc csredd csrede csredf
-                   csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7
-                   csree8 csree9 csreea csreeb csreec csreed csreee csreef
-                   csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7
-                   csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ];
-attach variables [ csr_F0 ]
-                 [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07
-                   csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f
-                   csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17
-                   csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f
-                   csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27
-                   csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f
-                   csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37
-                   csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f
-                   csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47
-                   csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f
-                   csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57
-                   csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f
-                   csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67
-                   csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f
-                   csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77
-                   csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ];
-attach variables [ csr_F8 ]
-                 [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87
-                   csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f
-                   csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97
-                   csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f
-                   csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7
-                   csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf
-                   csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7
-                   csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ];
-attach variables [ csr_FC ]
-                 [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7
-                   csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf
-                   csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7
-                   csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf
-                   csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7
-                   csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef
-                   csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7
-                   csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ];
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
index 480f1b6041..367f3d041b 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
@@ -226,9 +226,9 @@
 }
 
 # c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0) 
-:c.lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3
+:c.lui cd0711NoSp,cbigimm is cd0711NoSp & cbigimm & cop0001=0x1 & cop1315=0x3
 {
-	crd = cbigimm;
+	cd0711NoSp = cbigimm;
 }
 
 # c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4) 
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc
index f21ed223f0..bb37a6c42b 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc
@@ -41,19 +41,19 @@
 
 # vaadd.vv       31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vaadd.vv vd, vs2, vs1, vm   # roundoff_signed(vs2[i] + vs1[i], 1)
-:vaadd.vv  vd, vs2, vs1, vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vaadd.vv  vd, vs2, vs1^ vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vaadd.vx       31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vaadd.vx vd, vs2, rs1, vm   # roundoff_signed(vs2[i] + x[rs1], 1)
-:vaadd.vx  vd, vs2, rs1, vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vaadd.vx  vd, vs2, rs1^ vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vaaddu.vv      31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vaaddu.vv vd, vs2, vs1, vm   # roundoff_unsigned(vs2[i] + vs1[i], 1)
-:vaaddu.vv  vd, vs2, vs1, vm    is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vaaddu.vv  vd, vs2, vs1^ vm    is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vaaddu.vx      31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vaaddu.vx vd, vs2, rs1, vm   # roundoff_unsigned(vs2[i] + x[rs1], 1)
-:vaaddu.vx  vd, vs2, rs1, vm    is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vaaddu.vx  vd, vs2, rs1^ vm    is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vadc.vim       31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vadc.vim   vd, vs2, simm5, v0  # Vector-immediate
@@ -69,331 +69,331 @@
 
 # vadd.vi        31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vadd.vi vd, vs2, simm5, vm   # vector-immediate
-:vadd.vi  vd, vs2, simm5, vm    is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vadd.vi  vd, vs2, simm5^ vm    is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vadd.vv         31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vadd.vv vd, vs2, vs1, vm   # Vector-vector
-:vadd.vv  vd, vs2, vs1, vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vadd.vv  vd, vs2, vs1^ vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vadd.vx        31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vadd.vx vd, vs2, rs1, vm   # vector-scalar
-:vadd.vx  vd, vs2, rs1, vm    is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vadd.vx  vd, vs2, rs1^ vm    is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vamoaddei16.v  31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoaddei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoaddei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei16.v  31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoaddei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoaddei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei32.v  31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoaddei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoaddei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei32.v  31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoaddei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoaddei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei64.v  31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoaddei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoaddei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei64.v  31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoaddei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoaddei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei8.v   31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoaddei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoaddei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoaddei8.v   31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoaddei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoaddei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoaddei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei16.v  31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoandei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoandei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamoandei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei16.v  31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoandei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoandei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoandei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei32.v  31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoandei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoandei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamoandei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei32.v  31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoandei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoandei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamoandei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoandei64.v  31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoandei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoandei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamoandei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei64.v  31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoandei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoandei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamoandei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoandei8.v   31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoandei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoandei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamoandei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoandei8.v   31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoandei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoandei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamoandei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxei16.v  31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamomaxei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxei16.v  31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamomaxei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxei32.v  31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamomaxei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxei32.v  31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamomaxei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxei64.v  31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamomaxei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxei64.v  31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamomaxei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxei8.v   31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamomaxei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxei8.v   31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamomaxei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamomaxuei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxuei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxuei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamomaxuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxuei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxuei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamomaxuei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxuei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxuei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamomaxuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxuei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxuei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamomaxuei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxuei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxuei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamomaxuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxuei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxuei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamomaxuei8.v  31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamomaxuei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamomaxuei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamomaxuei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamomaxuei8.v  31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamomaxuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamomaxuei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamomaxuei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominei16.v  31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamominei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamominei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominei16.v  31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamominei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamominei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominei32.v  31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamominei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamominei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominei32.v  31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamominei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamominei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominei64.v  31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamominei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamominei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominei64.v  31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamominei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamominei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominei8.v   31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamominei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamominei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominei8.v   31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamominei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamominei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamominuei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominuei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamominuei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamominuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominuei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamominuei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamominuei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominuei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamominuei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamominuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominuei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamominuei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamominuei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominuei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamominuei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamominuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominuei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamominuei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamominuei8.v  31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamominuei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamominuei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamominuei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamominuei8.v  31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamominuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamominuei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamominuei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoorei16.v   31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoorei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoorei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamoorei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoorei16.v   31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoorei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamoorei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoorei32.v   31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoorei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoorei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamoorei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoorei32.v   31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoorei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamoorei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoorei64.v   31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoorei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoorei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamoorei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoorei64.v   31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoorei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamoorei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoorei8.v    31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoorei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoorei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamoorei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoorei8.v    31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoorei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamoorei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoswapei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoswapei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamoswapei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoswapei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoswapei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamoswapei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoswapei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoswapei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamoswapei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoswapei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoswapei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamoswapei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoswapei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoswapei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamoswapei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoswapei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoswapei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamoswapei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoswapei8.v  31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoswapei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoswapei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamoswapei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoswapei8.v  31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoswapei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoswapei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
+:vamoswapei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoxorei16.v  31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoxorei16.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoxorei16.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
+:vamoxorei16.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoxorei16.v  31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
 # vamoxorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoxorei16.v  zero, (rs1), vs2, vs3, vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
+:vamoxorei16.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoxorei32.v  31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoxorei32.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoxorei32.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
+:vamoxorei32.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoxorei32.v  31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
 # vamoxorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoxorei32.v  zero, (rs1), vs2, vs3, vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
+:vamoxorei32.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoxorei64.v  31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoxorei64.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoxorei64.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
+:vamoxorei64.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoxorei64.v  31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
 # vamoxorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoxorei64.v  zero, (rs1), vs2, vs3, vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
+:vamoxorei64.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f  unimpl
 
 # vamoxorei8.v   31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoxorei8.v vd, (rs1), vs2, vs3,  vm # Write original value to register, wd=1
-:vamoxorei8.v  vd, (rs1), vs2, vs3,  vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
+:vamoxorei8.v  vd, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f  unimpl
 
 # vamoxorei8.v   31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
 # vamoxorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
-:vamoxorei8.v  zero, (rs1), vs2, vs3, vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
+:vamoxorei8.v  zero, (rs1), vs2, vs3^ vm  is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f  unimpl
 
 # vand.vi        31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vand.vi vd, vs2, simm5, vm   # vector-immediate
-:vand.vi  vd, vs2, simm5, vm    is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vand.vi  vd, vs2, simm5^ vm    is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vand.vv         31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vand.vv vd, vs2, vs1, vm   # Vector-vector
-:vand.vv  vd, vs2, vs1, vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vand.vv  vd, vs2, vs1^ vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vand.vx        31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vand.vx vd, vs2, rs1, vm   # vector-scalar
-:vand.vx  vd, vs2, rs1, vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vand.vx  vd, vs2, rs1^ vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vasub.vv       31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vasub.vv vd, vs2, vs1, vm   # roundoff_signed(vs2[i] - vs1[i], 1)
-:vasub.vv  vd, vs2, vs1, vm    is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vasub.vv  vd, vs2, vs1^ vm    is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vasub.vx       31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vasub.vx vd, vs2, rs1, vm   # roundoff_signed(vs2[i] - x[rs1], 1)
-:vasub.vx  vd, vs2, rs1, vm    is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vasub.vx  vd, vs2, rs1^ vm    is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vasubu.vv      31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vasubu.vv vd, vs2, vs1, vm   # roundoff_unsigned(vs2[i] - vs1[i], 1)
-:vasubu.vv  vd, vs2, vs1, vm    is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vasubu.vv  vd, vs2, vs1^ vm    is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vasubu.vx      31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vasubu.vx vd, vs2, rs1, vm   # roundoff_unsigned(vs2[i] - x[rs1], 1)
-:vasubu.vx  vd, vs2, rs1, vm    is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vasubu.vx  vd, vs2, rs1^ vm    is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vcompress.vm   31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vcompress.vm vd, vs2, vs1  # Compress into vd elements of vs2 where vs1 is enabled
@@ -401,103 +401,103 @@
 
 # vdiv.vv        31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vdiv.vv vd, vs2, vs1, vm   # Vector-vector
-:vdiv.vv  vd, vs2, vs1, vm    is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vdiv.vv  vd, vs2, vs1^ vm    is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vdiv.vx        31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vdiv.vx vd, vs2, rs1, vm   # vector-scalar
-:vdiv.vx  vd, vs2, rs1, vm    is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vdiv.vx  vd, vs2, rs1^ vm    is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vdivu.vv       31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vdivu.vv vd, vs2, vs1, vm   # Vector-vector
-:vdivu.vv  vd, vs2, vs1, vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vdivu.vv  vd, vs2, vs1^ vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vdivu.vx       31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vdivu.vx vd, vs2, rs1, vm   # vector-scalar
-:vdivu.vx  vd, vs2, rs1, vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vdivu.vx  vd, vs2, rs1^ vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vdot.vv        31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vdot.vv vd, vs2, vs1, vm # Vector-vector
-:vdot.vv  vd, vs2, vs1, vm  is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vdot.vv  vd, vs2, vs1^ vm  is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vdotu.vv       31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vdotu.vv vd, vs2, vs1, vm # Vector-vector
-:vdotu.vv  vd, vs2, vs1, vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vdotu.vv  vd, vs2, vs1^ vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vfadd.vf        31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfadd.vf vd, vs2, rs1, vm   # vector-scalar
-:vfadd.vf  vd, vs2, rs1, vm    is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfadd.vf  vd, vs2, rs1^ vm    is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfadd.vv       31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfadd.vv vd, vs2, vs1, vm   # Vector-vector
-:vfadd.vv  vd, vs2, vs1, vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfadd.vv  vd, vs2, vs1^ vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfclass.v      31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
 # vfclass.v vd, vs2, vm   # Vector-vector
-:vfclass.v  vd, vs2, vm    is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfclass.v  vd, vs2^ vm    is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.f.x.v      31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57
 # vfcvt.f.x.v  vd, vs2, vm       # Convert signed integer to float.
-:vfcvt.f.x.v   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.f.x.v   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.f.xu.v     31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57
 # vfcvt.f.xu.v vd, vs2, vm       # Convert unsigned integer to float.
-:vfcvt.f.xu.v  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.f.xu.v  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.rtz.x.f.v  31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57
 # vfcvt.rtz.x.f.v  vd, vs2, vm   # Convert float to signed integer, truncating.
-:vfcvt.rtz.x.f.v   vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.rtz.x.f.v   vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57
 # vfcvt.rtz.xu.f.v vd, vs2, vm   # Convert float to unsigned integer, truncating.
-:vfcvt.rtz.xu.f.v  vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.rtz.xu.f.v  vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.x.f.v      31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57
 # vfcvt.x.f.v  vd, vs2, vm       # Convert float to signed integer.
-:vfcvt.x.f.v   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.x.f.v   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfcvt.xu.f.v     31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
 # vfcvt.xu.f.v vd, vs2, vm       # Convert float to unsigned integer.
-:vfcvt.xu.f.v  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfcvt.xu.f.v  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfdiv.vf       31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfdiv.vf vd, vs2, rs1, vm   # vector-scalar
-:vfdiv.vf  vd, vs2, rs1, vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfdiv.vf  vd, vs2, rs1^ vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfdiv.vv       31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfdiv.vv vd, vs2, vs1, vm   # Vector-vector
-:vfdiv.vv  vd, vs2, vs1, vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfdiv.vv  vd, vs2, vs1^ vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfdot.vv       31..26=0x39 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfdot.vv vd, vs2, vs1, vm # Vector-vector
-:vfdot.vv  vd, vs2, vs1, vm  is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfdot.vv  vd, vs2, vs1^ vm  is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfirst.m       31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57
 # vfirst.m rd, vs2, vm
-:vfirst.m  rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57  unimpl
+:vfirst.m  rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57  unimpl
 
 # vfmacc.vf      31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmacc.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) + vd[i]
-:vfmacc.vf  vd, rs1, vs2, vm     is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmacc.vf  vd, rs1, vs2^ vm     is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmacc.vv      31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vfmacc.vv  vd, vs1, vs2, vm     is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmacc.vv  vd, vs1, vs2^ vm     is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmadd.vf      31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmadd.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vd[i]) + vs2[i]
-:vfmadd.vf  vd, rs1, vs2, vm     is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmadd.vf  vd, rs1, vs2^ vm     is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmadd.vv      31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmadd.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vd[i]) + vs2[i]
-:vfmadd.vv  vd, vs1, vs2, vm     is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmadd.vv  vd, vs1, vs2^ vm     is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmax.vf        31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmax.vf vd, vs2, rs1, vm   # vector-scalar
-:vfmax.vf  vd, vs2, rs1, vm    is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmax.vf  vd, vs2, rs1^ vm    is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmax.vv       31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmax.vv vd, vs2, vs1, vm   # Vector-vector
-:vfmax.vv  vd, vs2, vs1, vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmax.vv  vd, vs2, vs1^ vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmerge.vfm    31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmerge.vfm vd, vs2, rs1, v0  # vd[i] = v0.mask[i] ? f[rs1] : vs2[i]
@@ -505,35 +505,35 @@
 
 # vfmin.vf        31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmin.vf vd, vs2, rs1, vm   # vector-scalar
-:vfmin.vf  vd, vs2, rs1, vm    is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmin.vf  vd, vs2, rs1^ vm    is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmin.vv       31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmin.vv vd, vs2, vs1, vm   # Vector-vector
-:vfmin.vv  vd, vs2, vs1, vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmin.vv  vd, vs2, vs1^ vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmsac.vf      31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmsac.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) - vd[i]
-:vfmsac.vf  vd, rs1, vs2, vm     is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmsac.vf  vd, rs1, vs2^ vm     is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmsac.vv      31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmsac.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) - vd[i]
-:vfmsac.vv  vd, vs1, vs2, vm     is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmsac.vv  vd, vs1, vs2^ vm     is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmsub.vf      31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmsub.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vd[i]) - vs2[i]
-:vfmsub.vf  vd, rs1, vs2, vm     is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmsub.vf  vd, rs1, vs2^ vm     is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmsub.vv      31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmsub.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vd[i]) - vs2[i]
-:vfmsub.vv  vd, vs1, vs2, vm     is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmsub.vv  vd, vs1, vs2^ vm     is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmul.vf       31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfmul.vf vd, vs2, rs1, vm   # vector-scalar
-:vfmul.vf  vd, vs2, rs1, vm    is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfmul.vf  vd, vs2, rs1^ vm    is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfmul.vv       31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfmul.vv vd, vs2, vs1, vm   # Vector-vector
-:vfmul.vv  vd, vs2, vs1, vm    is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfmul.vv  vd, vs2, vs1^ vm    is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfmv.f.s       31..26=0x10 25=1 vs2      19..15=0 14..12=0x1 rd 6..0=0x57
 # vfmv.f.s rd, vs2  # f[rd] = vs2[0] (rs1=0)
@@ -549,251 +549,251 @@
 
 # vfncvt.f.f.w      31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57
 # vfncvt.f.f.w vd, vs2, vm        # Convert double-width float to single-width float.
-:vfncvt.f.f.w  vd, vs2, vm         is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.f.f.w  vd, vs2^ vm         is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.f.x.w      31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57
 # vfncvt.f.x.w  vd, vs2, vm       # Convert double-width signed integer to float.
-:vfncvt.f.x.w   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.f.x.w   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.f.xu.w     31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57
 # vfncvt.f.xu.w vd, vs2, vm       # Convert double-width unsigned integer to float.
-:vfncvt.f.xu.w  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.f.xu.w  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.rod.f.f.w  31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57
 # vfncvt.rod.f.f.w vd, vs2, vm    # Convert double-width float to single-width float,
-:vfncvt.rod.f.f.w  vd, vs2, vm     is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.rod.f.f.w  vd, vs2^ vm     is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.rtz.x.f.w  31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57
 # vfncvt.rtz.x.f.w  vd, vs2, vm   # Convert double-width float to signed integer, truncating.
-:vfncvt.rtz.x.f.w   vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.rtz.x.f.w   vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57
 # vfncvt.rtz.xu.f.w vd, vs2, vm   # Convert double-width float to unsigned integer, truncating.
-:vfncvt.rtz.xu.f.w  vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.rtz.xu.f.w  vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.x.f.w      31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57
 # vfncvt.x.f.w  vd, vs2, vm       # Convert double-width float to signed integer.
-:vfncvt.x.f.w   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.x.f.w   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfncvt.xu.f.w     31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
 # vfncvt.xu.f.w vd, vs2, vm       # Convert double-width float to unsigned integer.
-:vfncvt.xu.f.w  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfncvt.xu.f.w  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfnmacc.vf     31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfnmacc.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) - vd[i]
-:vfnmacc.vf  vd, rs1, vs2, vm    is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfnmacc.vf  vd, rs1, vs2^ vm    is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfnmacc.vv     31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfnmacc.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) - vd[i]
-:vfnmacc.vv  vd, vs1, vs2, vm    is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfnmacc.vv  vd, vs1, vs2^ vm    is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfnmadd.vf     31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfnmadd.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vd[i]) - vs2[i]
-:vfnmadd.vf  vd, rs1, vs2, vm    is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfnmadd.vf  vd, rs1, vs2^ vm    is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfnmadd.vv     31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfnmadd.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vd[i]) - vs2[i]
-:vfnmadd.vv  vd, vs1, vs2, vm    is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfnmadd.vv  vd, vs1, vs2^ vm    is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfnmsac.vf     31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfnmsac.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) + vd[i]
-:vfnmsac.vf  vd, rs1, vs2, vm    is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfnmsac.vf  vd, rs1, vs2^ vm    is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfnmsac.vv     31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfnmsac.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
-:vfnmsac.vv  vd, vs1, vs2, vm    is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfnmsac.vv  vd, vs1, vs2^ vm    is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfnmsub.vf     31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfnmsub.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vd[i]) + vs2[i]
-:vfnmsub.vf  vd, rs1, vs2, vm    is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfnmsub.vf  vd, rs1, vs2^ vm    is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfnmsub.vv     31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfnmsub.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vd[i]) + vs2[i]
-:vfnmsub.vv  vd, vs1, vs2, vm    is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfnmsub.vv  vd, vs1, vs2^ vm    is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfrdiv.vf      31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfrdiv.vf vd, vs2, rs1, vm  # scalar-vector, vd[i] = f[rs1]/vs2[i]
-:vfrdiv.vf  vd, vs2, rs1, vm   is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfrdiv.vf  vd, vs2, rs1^ vm   is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfredmax.vs    31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfredmax.vs  vd, vs2, vs1, vm # Maximum value
-:vfredmax.vs   vd, vs2, vs1, vm  is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfredmax.vs   vd, vs2, vs1^ vm  is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfredmin.vs    31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfredmin.vs  vd, vs2, vs1, vm # Minimum value
-:vfredmin.vs   vd, vs2, vs1, vm  is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfredmin.vs   vd, vs2, vs1^ vm  is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfredosum.vs   31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfredosum.vs vd, vs2, vs1, vm # Ordered sum
-:vfredosum.vs  vd, vs2, vs1, vm  is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfredosum.vs  vd, vs2, vs1^ vm  is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfredsum.vs    31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfredsum.vs  vd, vs2, vs1, vm # Unordered sum
-:vfredsum.vs   vd, vs2, vs1, vm  is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfredsum.vs   vd, vs2, vs1^ vm  is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfrsub.vf      31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfrsub.vf vd, vs2, rs1, vm  # Scalar-vector vd[i] = f[rs1] - vs2[i]
-:vfrsub.vf  vd, vs2, rs1, vm   is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfrsub.vf  vd, vs2, rs1^ vm   is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsgnj.vf       31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfsgnj.vf vd, vs2, rs1, vm   # vector-scalar
-:vfsgnj.vf  vd, vs2, rs1, vm    is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfsgnj.vf  vd, vs2, rs1^ vm    is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsgnj.vv      31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfsgnj.vv vd, vs2, vs1, vm   # Vector-vector
-:vfsgnj.vv  vd, vs2, vs1, vm    is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfsgnj.vv  vd, vs2, vs1^ vm    is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfsgnjn.vf      31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfsgnjn.vf vd, vs2, rs1, vm   # vector-scalar
-:vfsgnjn.vf  vd, vs2, rs1, vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfsgnjn.vf  vd, vs2, rs1^ vm    is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsgnjn.vv     31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfsgnjn.vv vd, vs2, vs1, vm   # Vector-vector
-:vfsgnjn.vv  vd, vs2, vs1, vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfsgnjn.vv  vd, vs2, vs1^ vm    is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfsgnjx.vf      31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfsgnjx.vf vd, vs2, rs1, vm   # vector-scalar
-:vfsgnjx.vf  vd, vs2, rs1, vm    is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfsgnjx.vf  vd, vs2, rs1^ vm    is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsgnjx.vv     31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfsgnjx.vv vd, vs2, vs1, vm   # Vector-vector
-:vfsgnjx.vv  vd, vs2, vs1, vm    is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfsgnjx.vv  vd, vs2, vs1^ vm    is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfslide1down.vf vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
-:vfslide1down.vf  vd, vs2, rs1, vm       is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfslide1down.vf  vd, vs2, rs1^ vm       is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfslide1up.vf   31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfslide1up.vf vd, vs2, rs1, vm        # vd[0]=f[rs1], vd[i+1] = vs2[i]
-:vfslide1up.vf  vd, vs2, rs1, vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfslide1up.vf  vd, vs2, rs1^ vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsqrt.v       31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
 # vfsqrt.v vd, vs2, vm   # Vector-vector square root
-:vfsqrt.v  vd, vs2, vm    is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfsqrt.v  vd, vs2^ vm    is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfsub.vf        31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfsub.vf vd, vs2, rs1, vm   # Vector-scalar vd[i] = vs2[i] - f[rs1]
-:vfsub.vf  vd, vs2, rs1, vm    is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfsub.vf  vd, vs2, rs1^ vm    is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfsub.vv       31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfsub.vv vd, vs2, vs1, vm   # Vector-vector
-:vfsub.vv  vd, vs2, vs1, vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfsub.vv  vd, vs2, vs1^ vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwadd.vf      31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwadd.vf vd, vs2, rs1, vm  # vector-scalar
-:vfwadd.vf  vd, vs2, rs1, vm   is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwadd.vf  vd, vs2, rs1^ vm   is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwadd.vv      31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwadd.vv vd, vs2, vs1, vm  # vector-vector
-:vfwadd.vv  vd, vs2, vs1, vm   is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwadd.vv  vd, vs2, vs1^ vm   is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwadd.wf      31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwadd.wf  vd, vs2, rs1, vm  # vector-scalar
-:vfwadd.wf   vd, vs2, rs1, vm   is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwadd.wf   vd, vs2, rs1^ vm   is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwadd.wv      31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwadd.wv  vd, vs2, vs1, vm  # vector-vector
-:vfwadd.wv   vd, vs2, vs1, vm   is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwadd.wv   vd, vs2, vs1^ vm   is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.f.f.v      31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57
 # vfwcvt.f.f.v vd, vs2, vm        # Convert single-width float to double-width float.
-:vfwcvt.f.f.v  vd, vs2, vm         is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.f.f.v  vd, vs2^ vm         is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.f.x.v      31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57
 # vfwcvt.f.x.v  vd, vs2, vm       # Convert signed integer to double-width float.
-:vfwcvt.f.x.v   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.f.x.v   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.f.xu.v     31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57
 # vfwcvt.f.xu.v vd, vs2, vm       # Convert unsigned integer to double-width float.
-:vfwcvt.f.xu.v  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.f.xu.v  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.rtz.x.f.v  31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57
 # vfwcvt.rtz.x.f.v  vd, vs2, vm   # Convert float to double-width signed integer, truncating.
-:vfwcvt.rtz.x.f.v   vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.rtz.x.f.v   vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57
 # vfwcvt.rtz.xu.f.v vd, vs2, vm   # Convert float to double-width unsigned integer, truncating.
-:vfwcvt.rtz.xu.f.v  vd, vs2, vm    is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.rtz.xu.f.v  vd, vs2^ vm    is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.x.f.v      31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57
 # vfwcvt.x.f.v  vd, vs2, vm       # Convert float to double-width signed integer.
-:vfwcvt.x.f.v   vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.x.f.v   vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwcvt.xu.f.v     31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57
 # vfwcvt.xu.f.v vd, vs2, vm       # Convert float to double-width unsigned integer.
-:vfwcvt.xu.f.v  vd, vs2, vm        is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwcvt.xu.f.v  vd, vs2^ vm        is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwmacc.vf     31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwmacc.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) + vd[i]
-:vfwmacc.vf  vd, rs1, vs2, vm     is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwmacc.vf  vd, rs1, vs2^ vm     is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwmacc.vv     31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vfwmacc.vv  vd, vs1, vs2, vm     is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwmacc.vv  vd, vs1, vs2^ vm     is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwmsac.vf     31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwmsac.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) - vd[i]
-:vfwmsac.vf  vd, rs1, vs2, vm     is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwmsac.vf  vd, rs1, vs2^ vm     is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwmsac.vv     31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwmsac.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) - vd[i]
-:vfwmsac.vv  vd, vs1, vs2, vm     is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwmsac.vv  vd, vs1, vs2^ vm     is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwmul.vf      31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwmul.vf    vd, vs2, rs1, vm # vector-scalar
-:vfwmul.vf     vd, vs2, rs1, vm  is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwmul.vf     vd, vs2, rs1^ vm  is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwmul.vv      31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwmul.vv    vd, vs2, vs1, vm # vector-vector
-:vfwmul.vv     vd, vs2, vs1, vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwmul.vv     vd, vs2, vs1^ vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwnmacc.vf    31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwnmacc.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) - vd[i]
-:vfwnmacc.vf  vd, rs1, vs2, vm    is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwnmacc.vf  vd, rs1, vs2^ vm    is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwnmacc.vv    31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwnmacc.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) - vd[i]
-:vfwnmacc.vv  vd, vs1, vs2, vm    is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwnmacc.vv  vd, vs1, vs2^ vm    is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwnmsac.vf    31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwnmsac.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) + vd[i]
-:vfwnmsac.vf  vd, rs1, vs2, vm    is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwnmsac.vf  vd, rs1, vs2^ vm    is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwnmsac.vv    31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwnmsac.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
-:vfwnmsac.vv  vd, vs1, vs2, vm    is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwnmsac.vv  vd, vs1, vs2^ vm    is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwredosum.vs  31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwredosum.vs vd, vs2, vs1, vm # Ordered sum
-:vfwredosum.vs  vd, vs2, vs1, vm  is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwredosum.vs  vd, vs2, vs1^ vm  is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwredsum.vs   31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwredsum.vs vd, vs2, vs1, vm  # Unordered sum
-:vfwredsum.vs  vd, vs2, vs1, vm   is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwredsum.vs  vd, vs2, vs1^ vm   is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwsub.vf      31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwsub.vf vd, vs2, rs1, vm  # vector-scalar
-:vfwsub.vf  vd, vs2, rs1, vm   is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwsub.vf  vd, vs2, rs1^ vm   is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwsub.vv      31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwsub.vv vd, vs2, vs1, vm  # vector-vector
-:vfwsub.vv  vd, vs2, vs1, vm   is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwsub.vv  vd, vs2, vs1^ vm   is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vfwsub.wf      31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vfwsub.wf  vd, vs2, rs1, vm  # vector-scalar
-:vfwsub.wf   vd, vs2, rs1, vm   is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vfwsub.wf   vd, vs2, rs1^ vm   is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vfwsub.wv      31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vfwsub.wv  vd, vs2, vs1, vm  # vector-vector
-:vfwsub.wv   vd, vs2, vs1, vm   is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vfwsub.wv   vd, vs2, vs1^ vm   is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vid.v          31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57
 # vid.v vd, vm  # Write element ID to destination.
-:vid.v  vd, vm   is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vid.v  vd^ vm   is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # viota.m        31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57
 # viota.m vd, vs2, vm
-:viota.m  vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57  unimpl
+:viota.m  vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vl1re16.v      31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd  6..0=0x07
 # vl1re16.v  vd, (rs1)
@@ -861,139 +861,139 @@
 
 # vle1024.v      nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7  vd 6..0=0x07
 # vle1024.v vd, (rs1), vm  # 1024-bit unit-stride load
-:vle1024.v  vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vle1024.v  vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vle1024ff.v      nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7  vd 6..0=0x07
 # vle1024ff.v vd, (rs1), vm  # 1024-bit unit-stride fault-only-first load
-:vle1024ff.v  vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vle1024ff.v  vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vle128.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0  vd 6..0=0x07
 # vle128.v  vd, (rs1), vm  #  128-bit unit-stride load
-:vle128.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vle128.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vle128ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0  vd 6..0=0x07
 # vle128ff.v  vd, (rs1), vm  #  128-bit unit-stride fault-only-first load
-:vle128ff.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vle128ff.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vle16.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5  vd 6..0=0x07
 # vle16.v   vd, (rs1), vm  #   16-bit unit-stride load
-:vle16.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vle16.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vle16ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5  vd 6..0=0x07
 # vle16ff.v   vd, (rs1), vm  #   16-bit unit-stride fault-only-first load
-:vle16ff.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vle16ff.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vle256.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5  vd 6..0=0x07
 # vle256.v  vd, (rs1), vm  #  256-bit unit-stride load
-:vle256.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vle256.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vle256ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5  vd 6..0=0x07
 # vle256ff.v  vd, (rs1), vm  #  256-bit unit-stride fault-only-first load
-:vle256ff.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vle256ff.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vle32.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6  vd 6..0=0x07
 # vle32.v   vd, (rs1), vm  #   32-bit unit-stride load
-:vle32.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vle32.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vle32ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6  vd 6..0=0x07
 # vle32ff.v   vd, (rs1), vm  #   32-bit unit-stride fault-only-first load
-:vle32ff.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vle32ff.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vle512.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6  vd 6..0=0x07
 # vle512.v  vd, (rs1), vm  #  512-bit unit-stride load
-:vle512.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vle512.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vle512ff.v       nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6  vd 6..0=0x07
 # vle512ff.v  vd, (rs1), vm  #  512-bit unit-stride fault-only-first load
-:vle512ff.v   vd, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vle512ff.v   vd, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vle64.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7  vd 6..0=0x07
 # vle64.v   vd, (rs1), vm  #   64-bit unit-stride load
-:vle64.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vle64.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vle64ff.v        nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7  vd 6..0=0x07
 # vle64ff.v   vd, (rs1), vm  #   64-bit unit-stride fault-only-first load
-:vle64ff.v    vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vle64ff.v    vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vle8.v         nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0  vd 6..0=0x07
 # vle8.v    vd, (rs1), vm  #    8-bit unit-stride load
-:vle8.v     vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vle8.v     vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vle8ff.v         nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0  vd 6..0=0x07
 # vle8ff.v    vd, (rs1), vm  #    8-bit unit-stride fault-only-first load
-:vle8ff.v     vd, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vle8ff.v     vd, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vlse1024.v      nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7  vd 6..0=0x07
 # vlse1024.v vd, (rs1), rs2, vm  # 1024-bit strided load
-:vlse1024.v  vd, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vlse1024.v  vd, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vlse128.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0  vd 6..0=0x07
 # vlse128.v  vd, (rs1), rs2, vm  #  128-bit strided load
-:vlse128.v   vd, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vlse128.v   vd, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vlse16.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5  vd 6..0=0x07
 # vlse16.v   vd, (rs1), rs2, vm  #   16-bit strided load
-:vlse16.v    vd, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vlse16.v    vd, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vlse256.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5  vd 6..0=0x07
 # vlse256.v  vd, (rs1), rs2, vm  #  256-bit strided load
-:vlse256.v   vd, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vlse256.v   vd, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vlse32.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6  vd 6..0=0x07
 # vlse32.v   vd, (rs1), rs2, vm  #   32-bit strided load
-:vlse32.v    vd, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vlse32.v    vd, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vlse512.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6  vd 6..0=0x07
 # vlse512.v  vd, (rs1), rs2, vm  #  512-bit strided load
-:vlse512.v   vd, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vlse512.v   vd, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vlse64.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7  vd 6..0=0x07
 # vlse64.v   vd, (rs1), rs2, vm  #   64-bit strided load
-:vlse64.v    vd, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vlse64.v    vd, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vlse8.v         nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0  vd 6..0=0x07
 # vlse8.v    vd, (rs1), rs2, vm  #    8-bit strided load
-:vlse8.v     vd, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vlse8.v     vd, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vlxei1024.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
 # vlxei1024.v   vd, (rs1), vs2, vm  #   1024-bit indexed load of SEW data
-:vlxei1024.v    vd, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vlxei1024.v    vd, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vlxei128.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
 # vlxei128.v   vd, (rs1), vs2, vm  #   128-bit indexed load of SEW data
-:vlxei128.v    vd, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vlxei128.v    vd, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vlxei16.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
 # vlxei16.v   vd, (rs1), vs2, vm  #   16-bit indexed load of SEW data
-:vlxei16.v    vd, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vlxei16.v    vd, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vlxei256.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5  vd 6..0=0x07
 # vlxei256.v   vd, (rs1), vs2, vm  #   256-bit indexed load of SEW data
-:vlxei256.v    vd, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
+:vlxei256.v    vd, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7  unimpl
 
 # vlxei32.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
 # vlxei32.v   vd, (rs1), vs2, vm  #   32-bit indexed load of SEW data
-:vlxei32.v    vd, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vlxei32.v    vd, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vlxei512.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6  vd 6..0=0x07
 # vlxei512.v   vd, (rs1), vs2, vm  #   512-bit indexed load of SEW data
-:vlxei512.v    vd, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
+:vlxei512.v    vd, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7  unimpl
 
 # vlxei64.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7  vd 6..0=0x07
 # vlxei64.v   vd, (rs1), vs2, vm  #   64-bit indexed load of SEW data
-:vlxei64.v    vd, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
+:vlxei64.v    vd, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7  unimpl
 
 # vlxei8.v         nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0  vd 6..0=0x07
 # vlxei8.v    vd, (rs1), vs2, vm  #    8-bit indexed load of SEW data
-:vlxei8.v     vd, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
+:vlxei8.v     vd, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7  unimpl
 
 # vmacc.vv       31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vmacc.vv  vd, vs1, vs2, vm     is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmacc.vv  vd, vs1, vs2^ vm     is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmacc.vx       31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmacc.vx vd, rs1, vs2, vm    # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
-:vmacc.vx  vd, rs1, vs2, vm     is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmacc.vx  vd, rs1, vs2^ vm     is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmadc.vim      31..26=0x11 vm   vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmadc.vim   vd, vs2, simm5, v0  # Vector-immediate
@@ -1009,11 +1009,11 @@
 
 # vmadd.vv       31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmadd.vv vd, vs1, vs2, vm    # vd[i] = (vs1[i] * vd[i]) + vs2[i]
-:vmadd.vv  vd, vs1, vs2, vm     is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmadd.vv  vd, vs1, vs2^ vm     is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmadd.vx       31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmadd.vx vd, rs1, vs2, vm    # vd[i] = (x[rs1] * vd[i]) + vs2[i]
-:vmadd.vx  vd, rs1, vs2, vm     is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmadd.vx  vd, rs1, vs2^ vm     is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmand.mm       31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmand.mm vd, vs2, vs1     # vd[i] =   vs2.mask[i] &amp;&amp;  vs1.mask[i]
@@ -1025,19 +1025,19 @@
 
 # vmax.vv         31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmax.vv vd, vs2, vs1, vm   # Vector-vector
-:vmax.vv  vd, vs2, vs1, vm    is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmax.vv  vd, vs2, vs1^ vm    is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmax.vx        31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmax.vx vd, vs2, rs1, vm   # vector-scalar
-:vmax.vx  vd, vs2, rs1, vm    is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmax.vx  vd, vs2, rs1^ vm    is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmaxu.vv        31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmaxu.vv vd, vs2, vs1, vm   # Vector-vector
-:vmaxu.vv  vd, vs2, vs1, vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmaxu.vv  vd, vs2, vs1^ vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmaxu.vx       31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmaxu.vx vd, vs2, rs1, vm   # vector-scalar
-:vmaxu.vx  vd, vs2, rs1, vm    is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmaxu.vx  vd, vs2, rs1^ vm    is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmerge.vim     31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmerge.vim vd, vs2, simm5, v0  # vd[i] = v0.mask[i] ? imm    : vs2[i]
@@ -1053,59 +1053,59 @@
 
 # vmfeq.vf       31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmfeq.vf vd, vs2, rs1, vm  # vector-scalar
-:vmfeq.vf  vd, vs2, rs1, vm   is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmfeq.vf  vd, vs2, rs1^ vm   is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmfeq.vv       31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vmfeq.vv vd, vs2, vs1, vm  # Vector-vector
-:vmfeq.vv  vd, vs2, vs1, vm   is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vmfeq.vv  vd, vs2, vs1^ vm   is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vmfge.vf       31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmfge.vf vd, vs2, rs1, vm  # vector-scalar
-:vmfge.vf  vd, vs2, rs1, vm   is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmfge.vf  vd, vs2, rs1^ vm   is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmfgt.vf       31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmfgt.vf vd, vs2, rs1, vm  # vector-scalar
-:vmfgt.vf  vd, vs2, rs1, vm   is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmfgt.vf  vd, vs2, rs1^ vm   is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmfle.vf       31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmfle.vf vd, vs2, rs1, vm  # vector-scalar
-:vmfle.vf  vd, vs2, rs1, vm   is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmfle.vf  vd, vs2, rs1^ vm   is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmfle.vv       31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vmfle.vv vd, vs2, vs1, vm  # Vector-vector
-:vmfle.vv  vd, vs2, vs1, vm   is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vmfle.vv  vd, vs2, vs1^ vm   is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vmflt.vf       31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmflt.vf vd, vs2, rs1, vm  # vector-scalar
-:vmflt.vf  vd, vs2, rs1, vm   is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmflt.vf  vd, vs2, rs1^ vm   is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmflt.vv       31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vmflt.vv vd, vs2, vs1, vm  # Vector-vector
-:vmflt.vv  vd, vs2, vs1, vm   is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vmflt.vv  vd, vs2, vs1^ vm   is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vmfne.vf       31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
 # vmfne.vf vd, vs2, rs1, vm  # vector-scalar
-:vmfne.vf  vd, vs2, rs1, vm   is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
+:vmfne.vf  vd, vs2, rs1^ vm   is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57  unimpl
 
 # vmfne.vv       31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
 # vmfne.vv vd, vs2, vs1, vm  # Vector-vector
-:vmfne.vv  vd, vs2, vs1, vm   is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
+:vmfne.vv  vd, vs2, vs1^ vm   is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57  unimpl
 
 # vmin.vv         31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmin.vv vd, vs2, vs1, vm   # Vector-vector
-:vmin.vv  vd, vs2, vs1, vm    is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmin.vv  vd, vs2, vs1^ vm    is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmin.vx        31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmin.vx vd, vs2, rs1, vm   # vector-scalar
-:vmin.vx  vd, vs2, rs1, vm    is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmin.vx  vd, vs2, rs1^ vm    is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vminu.vv        31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vminu.vv vd, vs2, vs1, vm   # Vector-vector
-:vminu.vv  vd, vs2, vs1, vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vminu.vv  vd, vs2, vs1^ vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vminu.vx       31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vminu.vx vd, vs2, rs1, vm   # vector-scalar
-:vminu.vx  vd, vs2, rs1, vm    is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vminu.vx  vd, vs2, rs1^ vm    is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmnand.mm      31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmnand.mm vd, vs2, vs1    # vd[i] = !(vs2.mask[i] &amp;&amp;  vs1.mask[i])
@@ -1133,127 +1133,127 @@
 
 # vmsbf.m        31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57
 # vmsbf.m vd, vs2, vm
-:vmsbf.m  vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmsbf.m  vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmseq.vi       31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmseq.vi vd, vs2, simm5, vm  # vector-immediate
-:vmseq.vi  vd, vs2, simm5, vm   is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmseq.vi  vd, vs2, simm5^ vm   is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmseq.vv       31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmseq.vv vd, vs2, vs1, vm  # Vector-vector
-:vmseq.vv  vd, vs2, vs1, vm   is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmseq.vv  vd, vs2, vs1^ vm   is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmseq.vx       31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmseq.vx vd, vs2, rs1, vm  # vector-scalar
-:vmseq.vx  vd, vs2, rs1, vm   is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmseq.vx  vd, vs2, rs1^ vm   is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsgt.vi       31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmsgt.vi vd, vs2, simm5, vm    # Vector-immediate
-:vmsgt.vi  vd, vs2, simm5, vm     is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmsgt.vi  vd, vs2, simm5^ vm     is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmsgt.vx       31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsgt.vx vd, vs2, rs1, vm    # Vector-scalar
-:vmsgt.vx  vd, vs2, rs1, vm     is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsgt.vx  vd, vs2, rs1^ vm     is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsgtu.vi      31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmsgtu.vi vd, vs2, simm5, vm   # Vector-immediate
-:vmsgtu.vi  vd, vs2, simm5, vm    is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmsgtu.vi  vd, vs2, simm5^ vm    is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmsgtu.vx      31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsgtu.vx vd, vs2, rs1, vm   # Vector-scalar
-:vmsgtu.vx  vd, vs2, rs1, vm    is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsgtu.vx  vd, vs2, rs1^ vm    is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsif.m        31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57
 # vmsif.m vd, vs2, vm
-:vmsif.m  vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmsif.m  vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmsle.vi       31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmsle.vi vd, vs2, simm5, vm  # vector-immediate
-:vmsle.vi  vd, vs2, simm5, vm   is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmsle.vi  vd, vs2, simm5^ vm   is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmsle.vv       31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmsle.vv vd, vs2, vs1, vm  # Vector-vector
-:vmsle.vv  vd, vs2, vs1, vm   is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmsle.vv  vd, vs2, vs1^ vm   is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmsle.vx       31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsle.vx vd, vs2, rs1, vm  # vector-scalar
-:vmsle.vx  vd, vs2, rs1, vm   is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsle.vx  vd, vs2, rs1^ vm   is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsleu.vi      31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmsleu.vi vd, vs2, simm5, vm   # Vector-immediate
-:vmsleu.vi  vd, vs2, simm5, vm    is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmsleu.vi  vd, vs2, simm5^ vm    is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmsleu.vv      31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmsleu.vv vd, vs2, vs1, vm   # Vector-vector
-:vmsleu.vv  vd, vs2, vs1, vm    is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmsleu.vv  vd, vs2, vs1^ vm    is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmsleu.vx      31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsleu.vx vd, vs2, rs1, vm   # vector-scalar
-:vmsleu.vx  vd, vs2, rs1, vm    is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsleu.vx  vd, vs2, rs1^ vm    is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmslt.vv       31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmslt.vv vd, vs2, vs1, vm  # Vector-vector
-:vmslt.vv  vd, vs2, vs1, vm   is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmslt.vv  vd, vs2, vs1^ vm   is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmslt.vx       31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmslt.vx vd, vs2, rs1, vm  # vector-scalar
-:vmslt.vx  vd, vs2, rs1, vm   is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmslt.vx  vd, vs2, rs1^ vm   is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsltu.vv      31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmsltu.vv vd, vs2, vs1, vm  # Vector-vector
-:vmsltu.vv  vd, vs2, vs1, vm   is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmsltu.vv  vd, vs2, vs1^ vm   is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmsltu.vx      31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsltu.vx vd, vs2, rs1, vm  # Vector-scalar
-:vmsltu.vx  vd, vs2, rs1, vm   is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsltu.vx  vd, vs2, rs1^ vm   is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsne.vi       31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vmsne.vi vd, vs2, simm5, vm  # vector-immediate
-:vmsne.vi  vd, vs2, simm5, vm   is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vmsne.vi  vd, vs2, simm5^ vm   is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vmsne.vv       31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vmsne.vv vd, vs2, vs1, vm  # Vector-vector
-:vmsne.vv  vd, vs2, vs1, vm   is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vmsne.vv  vd, vs2, vs1^ vm   is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vmsne.vx       31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vmsne.vx vd, vs2, rs1, vm  # vector-scalar
-:vmsne.vx  vd, vs2, rs1, vm   is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vmsne.vx  vd, vs2, rs1^ vm   is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vmsof.m        31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57
 # vmsof.m vd, vs2, vm
-:vmsof.m  vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmsof.m  vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmul.vv        31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmul.vv vd, vs2, vs1, vm   # Vector-vector
-:vmul.vv  vd, vs2, vs1, vm    is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmul.vv  vd, vs2, vs1^ vm    is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmul.vx        31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmul.vx vd, vs2, rs1, vm   # vector-scalar
-:vmul.vx  vd, vs2, rs1, vm    is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmul.vx  vd, vs2, rs1^ vm    is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmulh.vv       31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmulh.vv vd, vs2, vs1, vm   # Vector-vector
-:vmulh.vv  vd, vs2, vs1, vm    is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmulh.vv  vd, vs2, vs1^ vm    is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmulh.vx       31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmulh.vx vd, vs2, rs1, vm   # vector-scalar
-:vmulh.vx  vd, vs2, rs1, vm    is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmulh.vx  vd, vs2, rs1^ vm    is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmulhsu.vv     31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmulhsu.vv vd, vs2, vs1, vm   # Vector-vector
-:vmulhsu.vv  vd, vs2, vs1, vm    is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmulhsu.vv  vd, vs2, vs1^ vm    is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmulhsu.vx     31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmulhsu.vx vd, vs2, rs1, vm   # vector-scalar
-:vmulhsu.vx  vd, vs2, rs1, vm    is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmulhsu.vx  vd, vs2, rs1^ vm    is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmulhu.vv      31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vmulhu.vv vd, vs2, vs1, vm   # Vector-vector
-:vmulhu.vv  vd, vs2, vs1, vm    is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vmulhu.vv  vd, vs2, vs1^ vm    is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vmulhu.vx      31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vmulhu.vx vd, vs2, rs1, vm   # vector-scalar
-:vmulhu.vx  vd, vs2, rs1, vm    is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vmulhu.vx  vd, vs2, rs1^ vm    is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vmv.s.x        31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57
 # vmv.s.x vd, rs1  # vd[0] = x[rs1] (vs2=0)
@@ -1303,187 +1303,187 @@
 #TODO  this is broken
 # vnclip.wi      31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vnclip.wi vd, vs2, simm5, vm  # vd[i] = clip(roundoff_signed(vs2[i], uimm5))
-:vnclip.wi  vd, vs2, simm5, vm   is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vnclip.wi  vd, vs2, simm5^ vm   is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vnclip.wv      31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vnclip.wv vd, vs2, vs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], vs1[i]))
-:vnclip.wv  vd, vs2, vs1, vm    is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vnclip.wv  vd, vs2, vs1^ vm    is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vnclip.wx      31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vnclip.wx vd, vs2, rs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], x[rs1]))
-:vnclip.wx  vd, vs2, rs1, vm    is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vnclip.wx  vd, vs2, rs1^ vm    is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vnclipu.wi     31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vnclipu.wi vd, vs2, simm5, vm  # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5))
-:vnclipu.wi  vd, vs2, simm5, vm   is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vnclipu.wi  vd, vs2, simm5^ vm   is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vnclipu.wv     31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vnclipu.wv vd, vs2, vs1, vm   # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i]))
-:vnclipu.wv  vd, vs2, vs1, vm    is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vnclipu.wv  vd, vs2, vs1^ vm    is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vnclipu.wx     31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vnclipu.wx vd, vs2, rs1, vm   # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1]))
-:vnclipu.wx  vd, vs2, rs1, vm    is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vnclipu.wx  vd, vs2, rs1^ vm    is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vnmsac.vv      31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vnmsac.vv vd, vs1, vs2, vm    # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
-:vnmsac.vv  vd, vs1, vs2, vm     is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vnmsac.vv  vd, vs1, vs2^ vm     is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vnmsac.vx      31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vnmsac.vx vd, rs1, vs2, vm    # vd[i] = -(x[rs1] * vs2[i]) + vd[i]
-:vnmsac.vx  vd, rs1, vs2, vm     is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vnmsac.vx  vd, rs1, vs2^ vm     is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vnmsub.vv      31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vnmsub.vv vd, vs1, vs2, vm    # vd[i] = -(vs1[i] * vd[i]) + vs2[i]
-:vnmsub.vv  vd, vs1, vs2, vm     is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vnmsub.vv  vd, vs1, vs2^ vm     is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vnmsub.vx      31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vnmsub.vx vd, rs1, vs2, vm    # vd[i] = -(x[rs1] * vd[i]) + vs2[i]
-:vnmsub.vx  vd, rs1, vs2, vm     is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vnmsub.vx  vd, rs1, vs2^ vm     is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vnsra.wi       31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vnsra.wi vd, vs2, simm5, vm   # vector-immediate
-:vnsra.wi  vd, vs2, simm5, vm    is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vnsra.wi  vd, vs2, simm5^ vm    is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vnsra.wv       31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vnsra.wv vd, vs2, vs1, vm   # vector-vector
-:vnsra.wv  vd, vs2, vs1, vm    is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vnsra.wv  vd, vs2, vs1^ vm    is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vnsra.wx       31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vnsra.wx vd, vs2, rs1, vm   # vector-scalar
-:vnsra.wx  vd, vs2, rs1, vm    is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vnsra.wx  vd, vs2, rs1^ vm    is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vnsrl.wi       31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vnsrl.wi vd, vs2, simm5, vm   # vector-immediate
-:vnsrl.wi  vd, vs2, simm5, vm    is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vnsrl.wi  vd, vs2, simm5^ vm    is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vnsrl.wv       31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vnsrl.wv vd, vs2, vs1, vm   # vector-vector
-:vnsrl.wv  vd, vs2, vs1, vm    is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vnsrl.wv  vd, vs2, vs1^ vm    is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vnsrl.wx       31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vnsrl.wx vd, vs2, rs1, vm   # vector-scalar
-:vnsrl.wx  vd, vs2, rs1, vm    is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vnsrl.wx  vd, vs2, rs1^ vm    is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vor.vi         31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vor.vi vd, vs2, simm5, vm    # vector-immediate
-:vor.vi  vd, vs2, simm5, vm     is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vor.vi  vd, vs2, simm5^ vm     is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vor.vv          31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vor.vv vd, vs2, vs1, vm    # Vector-vector
-:vor.vv  vd, vs2, vs1, vm     is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vor.vv  vd, vs2, vs1^ vm     is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vor.vx         31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vor.vx vd, vs2, rs1, vm    # vector-scalar
-:vor.vx  vd, vs2, rs1, vm     is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vor.vx  vd, vs2, rs1^ vm     is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vpopc.m        31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57
 # vpopc.m rd, vs2, vm # x[rd] = sum_i ( vs2.mask[i] &amp;&amp; v0.mask[i] )
-:vpopc.m  rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57  unimpl
+:vpopc.m  rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57  unimpl
 
 # vqmacc.vv      31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vqmacc.vv  vd, vs1, vs2, vm  is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vqmacc.vv  vd, vs1, vs2^ vm  is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vqmacc.vx      31..26=0x3d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
-:vqmacc.vx  vd, rs1, vs2, vm  is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vqmacc.vx  vd, rs1, vs2^ vm  is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vqmaccsu.vv    31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]
-:vqmaccsu.vv  vd, vs1, vs2, vm  is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vqmaccsu.vv  vd, vs1, vs2^ vm  is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vqmaccsu.vx    31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]
-:vqmaccsu.vx  vd, rs1, vs2, vm  is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vqmaccsu.vx  vd, rs1, vs2^ vm  is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vqmaccu.vv     31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vqmaccu.vv  vd, vs1, vs2, vm  is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vqmaccu.vv  vd, vs1, vs2^ vm  is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vqmaccu.vx     31..26=0x3c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
-:vqmaccu.vx  vd, rs1, vs2, vm  is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vqmaccu.vx  vd, rs1, vs2^ vm  is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vqmaccus.vx    31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
-:vqmaccus.vx  vd, rs1, vs2, vm  is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vqmaccus.vx  vd, rs1, vs2^ vm  is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vredand.vs     31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredand.vs  vd, vs2, vs1, vm   # vd[0] =  and( vs1[0] , vs2[*] )
-:vredand.vs   vd, vs2, vs1, vm    is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredand.vs   vd, vs2, vs1^ vm    is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredmax.vs     31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredmax.vs  vd, vs2, vs1, vm   # vd[0] =  max( vs1[0] , vs2[*] )
-:vredmax.vs   vd, vs2, vs1, vm    is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredmax.vs   vd, vs2, vs1^ vm    is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredmaxu.vs    31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredmaxu.vs vd, vs2, vs1, vm   # vd[0] = maxu( vs1[0] , vs2[*] )
-:vredmaxu.vs  vd, vs2, vs1, vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredmaxu.vs  vd, vs2, vs1^ vm    is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredmin.vs     31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredmin.vs  vd, vs2, vs1, vm   # vd[0] =  min( vs1[0] , vs2[*] )
-:vredmin.vs   vd, vs2, vs1, vm    is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredmin.vs   vd, vs2, vs1^ vm    is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredminu.vs    31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredminu.vs vd, vs2, vs1, vm   # vd[0] = minu( vs1[0] , vs2[*] )
-:vredminu.vs  vd, vs2, vs1, vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredminu.vs  vd, vs2, vs1^ vm    is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredor.vs      31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredor.vs   vd, vs2, vs1, vm   # vd[0] =   or( vs1[0] , vs2[*] )
-:vredor.vs    vd, vs2, vs1, vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredor.vs    vd, vs2, vs1^ vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredsum.vs     31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredsum.vs  vd, vs2, vs1, vm   # vd[0] =  sum( vs1[0] , vs2[*] )
-:vredsum.vs   vd, vs2, vs1, vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredsum.vs   vd, vs2, vs1^ vm    is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vredxor.vs     31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vredxor.vs  vd, vs2, vs1, vm   # vd[0] =  xor( vs1[0] , vs2[*] )
-:vredxor.vs   vd, vs2, vs1, vm    is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vredxor.vs   vd, vs2, vs1^ vm    is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vrem.vv        31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vrem.vv vd, vs2, vs1, vm   # Vector-vector
-:vrem.vv  vd, vs2, vs1, vm    is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vrem.vv  vd, vs2, vs1^ vm    is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vrem.vx        31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vrem.vx vd, vs2, rs1, vm   # vector-scalar
-:vrem.vx  vd, vs2, rs1, vm    is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vrem.vx  vd, vs2, rs1^ vm    is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vremu.vv       31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vremu.vv vd, vs2, vs1, vm   # Vector-vector
-:vremu.vv  vd, vs2, vs1, vm    is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vremu.vv  vd, vs2, vs1^ vm    is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vremu.vx       31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vremu.vx vd, vs2, rs1, vm   # vector-scalar
-:vremu.vx  vd, vs2, rs1, vm    is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vremu.vx  vd, vs2, rs1^ vm    is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vrgather.vi    31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vrgather.vi vd, vs2, simm5, vm # vd[i] = (uimm &gt;= VLMAX) ? 0 : vs2[uimm]
-:vrgather.vi  vd, vs2, simm5, vm  is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vrgather.vi  vd, vs2, simm5^ vm  is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vrgather.vv     31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] &gt;= VLMAX) ? 0 : vs2[vs1[i]];
-:vrgather.vv  vd, vs2, vs1, vm  is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vrgather.vv  vd, vs2, vs1^ vm  is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vrgather.vx    31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] &gt;= VLMAX) ? 0 : vs2[x[rs1]]
-:vrgather.vx  vd, vs2, rs1, vm  is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vrgather.vx  vd, vs2, rs1^ vm  is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] &gt;= VLMAX) ? 0 : vs2[vs1[i]];
-:vrgatherei16.vv  vd, vs2, vs1, vm  is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vrgatherei16.vv  vd, vs2, vs1^ vm  is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vrsub.vi       31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vrsub.vi vd, vs2, simm5, vm   # vd[i] = imm - vs2[i]
-:vrsub.vi  vd, vs2, simm5, vm    is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vrsub.vi  vd, vs2, simm5^ vm    is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vrsub.vx       31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vrsub.vx vd, vs2, rs1, vm   # vd[i] = rs1 - vs2[i]
-:vrsub.vx  vd, vs2, rs1, vm    is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vrsub.vx  vd, vs2, rs1^ vm    is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vs1r.v         31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
 # vs1r.v   vs3, (rs1)
@@ -1503,27 +1503,27 @@
 
 # vsadd.vi       31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vsadd.vi vd, vs2, simm5, vm   # vector-immediate
-:vsadd.vi  vd, vs2, simm5, vm    is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vsadd.vi  vd, vs2, simm5^ vm    is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vsadd.vv       31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsadd.vv vd, vs2, vs1, vm   # Vector-vector
-:vsadd.vv  vd, vs2, vs1, vm    is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsadd.vv  vd, vs2, vs1^ vm    is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsadd.vx       31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsadd.vx vd, vs2, rs1, vm   # vector-scalar
-:vsadd.vx  vd, vs2, rs1, vm    is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsadd.vx  vd, vs2, rs1^ vm    is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsaddu.vi      31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vsaddu.vi vd, vs2, simm5, vm   # vector-immediate
-:vsaddu.vi  vd, vs2, simm5, vm    is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vsaddu.vi  vd, vs2, simm5^ vm    is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vsaddu.vv      31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsaddu.vv vd, vs2, vs1, vm   # Vector-vector
-:vsaddu.vv  vd, vs2, vs1, vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsaddu.vv  vd, vs2, vs1^ vm    is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsaddu.vx      31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsaddu.vx vd, vs2, rs1, vm   # vector-scalar
-:vsaddu.vx  vd, vs2, rs1, vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsaddu.vx  vd, vs2, rs1^ vm    is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsbc.vvm       31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsbc.vvm   vd, vs2, vs1, v0  # Vector-vector
@@ -1535,35 +1535,35 @@
 
 # vse1024.v      nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
 # vse1024.v vs3, (rs1), vm  # 1024-bit unit-stride store
-:vse1024.v  vs3, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vse1024.v  vs3, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vse128.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
 # vse128.v  vs3, (rs1), vm  #  128-bit unit-stride store
-:vse128.v   vs3, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vse128.v   vs3, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vse16.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
 # vse16.v   vs3, (rs1), vm  #   16-bit unit-stride store
-:vse16.v    vs3, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vse16.v    vs3, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vse256.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
 # vse256.v  vs3, (rs1), vm  #  256-bit unit-stride store
-:vse256.v   vs3, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vse256.v   vs3, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vse32.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
 # vse32.v   vs3, (rs1), vm  #   32-bit unit-stride store
-:vse32.v    vs3, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vse32.v    vs3, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vse512.v       nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
 # vse512.v  vs3, (rs1), vm  #  512-bit unit-stride store
-:vse512.v   vs3, (rs1), vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vse512.v   vs3, (rs1)^ vm   is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vse64.v        nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
 # vse64.v   vs3, (rs1), vm  #   64-bit unit-stride store
-:vse64.v    vs3, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vse64.v    vs3, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vse8.v         nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
 # vse8.v    vs3, (rs1), vm  #    8-bit unit-stride store
-:vse8.v     vs3, (rs1), vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vse8.v     vs3, (rs1)^ vm   is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vsetvl       31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57
 # vsetvl  rd, rs1, rs2    # rd = new vl, rs1 = AVL, rs2 = new vtype value
@@ -1576,380 +1576,380 @@
 
 # vsext.vf2      31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57
 # vsext.vf2 vd, vs2, vm  # Sign-extend SEW/2 source to SEW destination
-:vsext.vf2  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vsext.vf2  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vsext.vf4      31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57
 # vsext.vf4 vd, vs2, vm  # Sign-extend SEW/4 source to SEW destination
-:vsext.vf4  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vsext.vf4  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vsext.vf8      31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57
 # vsext.vf8 vd, vs2, vm  # Sign-extend SEW/8 source to SEW destination
-:vsext.vf8  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vsext.vf8  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vslide1down.vx  vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
-:vslide1down.vx   vd, vs2, rs1, vm       is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vslide1down.vx   vd, vs2, rs1^ vm       is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vslide1up.vx   31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vslide1up.vx  vd, vs2, rs1, vm        # vd[0]=x[rs1], vd[i+1] = vs2[i]
-:vslide1up.vx   vd, vs2, rs1, vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vslide1up.vx   vd, vs2, rs1^ vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vslidedown.vi  31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vslidedown.vi vd, vs2, simm5[4:0], vm # vd[i] = vs2[i+uimm]
-:vslidedown.vi  vd, vs2, simm5[4:0], vm  is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vslidedown.vi  vd, vs2, simm5[4:0]^ vm  is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vslidedown.vx  31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vslidedown.vx vd, vs2, rs1, vm       # vd[i] = vs2[i+rs1]
-:vslidedown.vx  vd, vs2, rs1, vm        is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vslidedown.vx  vd, vs2, rs1^ vm        is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vslideup.vi    31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vslideup.vi vd, vs2, simm5[4:0], vm  # vd[i+uimm] = vs2[i]
-:vslideup.vi  vd, vs2, simm5[4:0], vm   is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vslideup.vi  vd, vs2, simm5[4:0]^ vm   is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vslideup.vx    31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vslideup.vx vd, vs2, rs1, vm        # vd[i+rs1] = vs2[i]
-:vslideup.vx  vd, vs2, rs1, vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vslideup.vx  vd, vs2, rs1^ vm         is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vsll.vi        31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vsll.vi vd, vs2, simm5, vm   # vector-immediate
-:vsll.vi  vd, vs2, simm5, vm    is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vsll.vi  vd, vs2, simm5^ vm    is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vsll.vv        31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsll.vv vd, vs2, vs1, vm   # Vector-vector
-:vsll.vv  vd, vs2, vs1, vm    is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsll.vv  vd, vs2, vs1^ vm    is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsll.vx        31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsll.vx vd, vs2, rs1, vm   # vector-scalar
-:vsll.vx  vd, vs2, rs1, vm    is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsll.vx  vd, vs2, rs1^ vm    is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsmul.vv       31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsmul.vv vd, vs2, vs1, vm  # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1))
-:vsmul.vv  vd, vs2, vs1, vm   is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsmul.vv  vd, vs2, vs1^ vm   is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsmul.vx       31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsmul.vx vd, vs2, rs1, vm  # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))
-:vsmul.vx  vd, vs2, rs1, vm   is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsmul.vx  vd, vs2, rs1^ vm   is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #OTOD  this is broken
 # vsra.vi        31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vsra.vi vd, vs2, simm5, vm   # vector-immediate
-:vsra.vi  vd, vs2, simm5, vm    is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vsra.vi  vd, vs2, simm5^ vm    is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vsra.vv        31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsra.vv vd, vs2, vs1, vm   # Vector-vector
-:vsra.vv  vd, vs2, vs1, vm    is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsra.vv  vd, vs2, vs1^ vm    is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsra.vx        31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsra.vx vd, vs2, rs1, vm   # vector-scalar
-:vsra.vx  vd, vs2, rs1, vm    is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsra.vx  vd, vs2, rs1^ vm    is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vsrl.vi        31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vsrl.vi vd, vs2, simm5, vm   # vector-immediate
-:vsrl.vi  vd, vs2, simm5, vm    is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vsrl.vi  vd, vs2, simm5^ vm    is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vsrl.vv        31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsrl.vv vd, vs2, vs1, vm   # Vector-vector
-:vsrl.vv  vd, vs2, vs1, vm    is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsrl.vv  vd, vs2, vs1^ vm    is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsrl.vx        31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsrl.vx vd, vs2, rs1, vm   # vector-scalar
-:vsrl.vx  vd, vs2, rs1, vm    is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsrl.vx  vd, vs2, rs1^ vm    is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsse1024.v      nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsse1024.v vs3, (rs1), rs2, vm  # 1024-bit strided store
-:vsse1024.v  vs3, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsse1024.v  vs3, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsse128.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsse128.v  vs3, (rs1), rs2, vm  #  128-bit strided store
-:vsse128.v   vs3, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsse128.v   vs3, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vsse16.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsse16.v   vs3, (rs1), rs2, vm  #   16-bit strided store
-:vsse16.v    vs3, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsse16.v    vs3, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsse256.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsse256.v  vs3, (rs1), rs2, vm  #  256-bit strided store
-:vsse256.v   vs3, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsse256.v   vs3, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsse32.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsse32.v   vs3, (rs1), rs2, vm  #   32-bit strided store
-:vsse32.v    vs3, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsse32.v    vs3, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsse512.v       nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsse512.v  vs3, (rs1), rs2, vm  #  512-bit strided store
-:vsse512.v   vs3, (rs1), rs2, vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsse512.v   vs3, (rs1), rs2^ vm   is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsse64.v        nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsse64.v   vs3, (rs1), rs2, vm  #   64-bit strided store
-:vsse64.v    vs3, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsse64.v    vs3, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsse8.v         nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsse8.v    vs3, (rs1), rs2, vm  #    8-bit strided store
-:vsse8.v     vs3, (rs1), rs2, vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsse8.v     vs3, (rs1), rs2^ vm   is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 #TODO  this is broken
 # vssra.vi       31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vssra.vi vd, vs2, simm5, vm   # vd[i] = roundoff_signed(vs2[i], uimm)
-:vssra.vi  vd, vs2, simm5, vm    is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vssra.vi  vd, vs2, simm5^ vm    is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vssra.vv       31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vssra.vv vd, vs2, vs1, vm   # vd[i] = roundoff_signed(vs2[i],vs1[i])
-:vssra.vv  vd, vs2, vs1, vm    is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vssra.vv  vd, vs2, vs1^ vm    is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vssra.vx       31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vssra.vx vd, vs2, rs1, vm   # vd[i] = roundoff_signed(vs2[i], x[rs1])
-:vssra.vx  vd, vs2, rs1, vm    is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vssra.vx  vd, vs2, rs1^ vm    is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 #TODO  this is broken
 # vssrl.vi       31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vssrl.vi vd, vs2, simm5, vm   # vd[i] = roundoff_unsigned(vs2[i], uimm)
-:vssrl.vi  vd, vs2, simm5, vm    is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vssrl.vi  vd, vs2, simm5^ vm    is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vssrl.vv       31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vssrl.vv vd, vs2, vs1, vm   # vd[i] = roundoff_unsigned(vs2[i], vs1[i])
-:vssrl.vv  vd, vs2, vs1, vm    is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vssrl.vv  vd, vs2, vs1^ vm    is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vssrl.vx       31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vssrl.vx vd, vs2, rs1, vm   # vd[i] = roundoff_unsigned(vs2[i], x[rs1])
-:vssrl.vx  vd, vs2, rs1, vm    is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vssrl.vx  vd, vs2, rs1^ vm    is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vssub.vv       31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vssub.vv vd, vs2, vs1, vm   # Vector-vector
-:vssub.vv  vd, vs2, vs1, vm    is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vssub.vv  vd, vs2, vs1^ vm    is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vssub.vx       31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vssub.vx vd, vs2, rs1, vm   # vector-scalar
-:vssub.vx  vd, vs2, rs1, vm    is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vssub.vx  vd, vs2, rs1^ vm    is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vssubu.vv      31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vssubu.vv vd, vs2, vs1, vm   # Vector-vector
-:vssubu.vv  vd, vs2, vs1, vm    is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vssubu.vv  vd, vs2, vs1^ vm    is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vssubu.vx      31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vssubu.vx vd, vs2, rs1, vm   # vector-scalar
-:vssubu.vx  vd, vs2, rs1, vm    is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vssubu.vx  vd, vs2, rs1^ vm    is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsub.vv         31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vsub.vv vd, vs2, vs1, vm   # Vector-vector
-:vsub.vv  vd, vs2, vs1, vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vsub.vv  vd, vs2, vs1^ vm    is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vsub.vx        31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vsub.vx vd, vs2, rs1, vm   # vector-scalar
-:vsub.vx  vd, vs2, rs1, vm    is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vsub.vx  vd, vs2, rs1^ vm    is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vsuxei1024.v     nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsuxei1024.v  vs3, (rs1), vs2, vm # unordered 1024-bit indexed store of SEW data
-:vsuxei1024.v   vs3, (rs1), vs2, vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsuxei1024.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsuxei128.v      nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsuxei128.v  vs3, (rs1), vs2, vm # unordered 128-bit indexed store of SEW data
-:vsuxei128.v   vs3, (rs1), vs2, vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsuxei128.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vsuxei16.v       nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsuxei16.v  vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data
-:vsuxei16.v   vs3, (rs1), vs2, vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsuxei16.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsuxei256.v      nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsuxei256.v  vs3, (rs1), vs2, vm # unordered 256-bit indexed store of SEW data
-:vsuxei256.v   vs3, (rs1), vs2, vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsuxei256.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsuxei32.v       nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsuxei32.v  vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data
-:vsuxei32.v   vs3, (rs1), vs2, vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsuxei32.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsuxei512.v      nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsuxei512.v  vs3, (rs1), vs2, vm # unordered 512-bit indexed store of SEW data
-:vsuxei512.v   vs3, (rs1), vs2, vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsuxei512.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsuxei64.v       nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsuxei64.v  vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data
-:vsuxei64.v   vs3, (rs1), vs2, vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsuxei64.v   vs3, (rs1), vs2^ vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsuxei8.v        nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsuxei8.v   vs3, (rs1), vs2, vm # unordered  8-bit indexed store of SEW data
-:vsuxei8.v    vs3, (rs1), vs2, vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsuxei8.v    vs3, (rs1), vs2^ vm  is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vsxei1024.v      nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsxei1024.v   vs3, (rs1), vs2, vm  # ordered 1024-bit indexed store of SEW data
-:vsxei1024.v    vs3, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsxei1024.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsxei128.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsxei128.v   vs3, (rs1), vs2, vm  # ordered 128-bit indexed store of SEW data
-:vsxei128.v    vs3, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsxei128.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vsxei16.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsxei16.v   vs3, (rs1), vs2, vm  # ordered 16-bit indexed store of SEW data
-:vsxei16.v    vs3, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsxei16.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsxei256.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
 # vsxei256.v   vs3, (rs1), vs2, vm  # ordered 256-bit indexed store of SEW data
-:vsxei256.v    vs3, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
+:vsxei256.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27  unimpl
 
 # vsxei32.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsxei32.v   vs3, (rs1), vs2, vm  # ordered 32-bit indexed store of SEW data
-:vsxei32.v    vs3, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsxei32.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsxei512.v       nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
 # vsxei512.v   vs3, (rs1), vs2, vm  # ordered 512-bit indexed store of SEW data
-:vsxei512.v    vs3, (rs1), vs2, vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
+:vsxei512.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27  unimpl
 
 # vsxei64.v        nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
 # vsxei64.v   vs3, (rs1), vs2, vm  # ordered 64-bit indexed store of SEW data
-:vsxei64.v    vs3, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
+:vsxei64.v    vs3, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27  unimpl
 
 # vsxei8.v         nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
 # vsxei8.v    vs3, (rs1), vs2, vm  # ordered  8-bit indexed store of SEW data
-:vsxei8.v     vs3, (rs1), vs2, vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
+:vsxei8.v     vs3, (rs1), vs2^ vm   is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27  unimpl
 
 # vwadd.vv       31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwadd.vv  vd, vs2, vs1, vm  # vector-vector
-:vwadd.vv   vd, vs2, vs1, vm   is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwadd.vv   vd, vs2, vs1^ vm   is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwadd.vx       31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwadd.vx  vd, vs2, rs1, vm  # vector-scalar
-:vwadd.vx   vd, vs2, rs1, vm   is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwadd.vx   vd, vs2, rs1^ vm   is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwadd.wv       31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwadd.wv  vd, vs2, vs1, vm  # vector-vector
-:vwadd.wv   vd, vs2, vs1, vm   is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwadd.wv   vd, vs2, vs1^ vm   is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwadd.wx       31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwadd.wx  vd, vs2, rs1, vm  # vector-scalar
-:vwadd.wx   vd, vs2, rs1, vm   is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwadd.wx   vd, vs2, rs1^ vm   is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwaddu.vv      31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwaddu.vv  vd, vs2, vs1, vm  # vector-vector
-:vwaddu.vv   vd, vs2, vs1, vm   is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwaddu.vv   vd, vs2, vs1^ vm   is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwaddu.vx      31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwaddu.vx  vd, vs2, rs1, vm  # vector-scalar
-:vwaddu.vx   vd, vs2, rs1, vm   is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwaddu.vx   vd, vs2, rs1^ vm   is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwaddu.wv      31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwaddu.wv  vd, vs2, vs1, vm  # vector-vector
-:vwaddu.wv   vd, vs2, vs1, vm   is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwaddu.wv   vd, vs2, vs1^ vm   is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwaddu.wx      31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwaddu.wx  vd, vs2, rs1, vm  # vector-scalar
-:vwaddu.wx   vd, vs2, rs1, vm   is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwaddu.wx   vd, vs2, rs1^ vm   is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmacc.vv      31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vwmacc.vv  vd, vs1, vs2, vm     is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmacc.vv  vd, vs1, vs2^ vm     is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmacc.vx      31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmacc.vx vd, rs1, vs2, vm    # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
-:vwmacc.vx  vd, rs1, vs2, vm     is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmacc.vx  vd, rs1, vs2^ vm     is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmaccsu.vv    31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmaccsu.vv vd, vs1, vs2, vm    # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]
-:vwmaccsu.vv  vd, vs1, vs2, vm     is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmaccsu.vv  vd, vs1, vs2^ vm     is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmaccsu.vx    31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmaccsu.vx vd, rs1, vs2, vm    # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]
-:vwmaccsu.vx  vd, rs1, vs2, vm     is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmaccsu.vx  vd, rs1, vs2^ vm     is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmaccu.vv     31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmaccu.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
-:vwmaccu.vv  vd, vs1, vs2, vm     is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmaccu.vv  vd, vs1, vs2^ vm     is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmaccu.vx     31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmaccu.vx vd, rs1, vs2, vm    # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
-:vwmaccu.vx  vd, rs1, vs2, vm     is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmaccu.vx  vd, rs1, vs2^ vm     is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmaccus.vx    31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmaccus.vx vd, rs1, vs2, vm    # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
-:vwmaccus.vx  vd, rs1, vs2, vm     is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmaccus.vx  vd, rs1, vs2^ vm     is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmul.vv       31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmul.vv  vd, vs2, vs1, vm# vector-vector
-:vwmul.vv   vd, vs2, vs1, vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmul.vv   vd, vs2, vs1^ vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmul.vx       31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmul.vx  vd, vs2, rs1, vm # vector-scalar
-:vwmul.vx   vd, vs2, rs1, vm  is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmul.vx   vd, vs2, rs1^ vm  is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmulsu.vv     31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmulsu.vv vd, vs2, vs1, vm # vector-vector
-:vwmulsu.vv  vd, vs2, vs1, vm  is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmulsu.vv  vd, vs2, vs1^ vm  is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmulsu.vx     31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmulsu.vx vd, vs2, rs1, vm # vector-scalar
-:vwmulsu.vx  vd, vs2, rs1, vm  is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmulsu.vx  vd, vs2, rs1^ vm  is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwmulu.vv      31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwmulu.vv vd, vs2, vs1, vm # vector-vector
-:vwmulu.vv  vd, vs2, vs1, vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwmulu.vv  vd, vs2, vs1^ vm  is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwmulu.vx      31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwmulu.vx vd, vs2, rs1, vm # vector-scalar
-:vwmulu.vx  vd, vs2, rs1, vm  is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwmulu.vx  vd, vs2, rs1^ vm  is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwredsum.vs    31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vwredsum.vs  vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(sign-extend(SEW))
-:vwredsum.vs   vd, vs2, vs1, vm    is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vwredsum.vs   vd, vs2, vs1^ vm    is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vwredsumu.vs   31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vwredsumu.vs vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(zero-extend(SEW))
-:vwredsumu.vs  vd, vs2, vs1, vm    is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vwredsumu.vs  vd, vs2, vs1^ vm    is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vwsub.vv       31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwsub.vv  vd, vs2, vs1, vm  # vector-vector
-:vwsub.vv   vd, vs2, vs1, vm   is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwsub.vv   vd, vs2, vs1^ vm   is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwsub.vx       31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwsub.vx  vd, vs2, rs1, vm  # vector-scalar
-:vwsub.vx   vd, vs2, rs1, vm   is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwsub.vx   vd, vs2, rs1^ vm   is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwsub.wv       31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwsub.wv  vd, vs2, vs1, vm  # vector-vector
-:vwsub.wv   vd, vs2, vs1, vm   is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwsub.wv   vd, vs2, vs1^ vm   is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwsub.wx       31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwsub.wx  vd, vs2, rs1, vm  # vector-scalar
-:vwsub.wx   vd, vs2, rs1, vm   is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwsub.wx   vd, vs2, rs1^ vm   is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwsubu.vv      31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwsubu.vv  vd, vs2, vs1, vm  # vector-vector
-:vwsubu.vv   vd, vs2, vs1, vm   is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwsubu.vv   vd, vs2, vs1^ vm   is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwsubu.vx      31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwsubu.vx  vd, vs2, rs1, vm  # vector-scalar
-:vwsubu.vx   vd, vs2, rs1, vm   is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwsubu.vx   vd, vs2, rs1^ vm   is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vwsubu.wv      31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
 # vwsubu.wv  vd, vs2, vs1, vm  # vector-vector
-:vwsubu.wv   vd, vs2, vs1, vm   is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vwsubu.wv   vd, vs2, vs1^ vm   is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vwsubu.wx      31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
 # vwsubu.wx  vd, vs2, rs1, vm  # vector-scalar
-:vwsubu.wx   vd, vs2, rs1, vm   is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
+:vwsubu.wx   vd, vs2, rs1^ vm   is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57  unimpl
 
 # vxor.vi        31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
 # vxor.vi vd, vs2, simm5, vm    # vector-immediate
-:vxor.vi  vd, vs2, simm5, vm     is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
+:vxor.vi  vd, vs2, simm5^ vm     is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57  unimpl
 
 # vxor.vv         31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
 # vxor.vv vd, vs2, vs1, vm    # Vector-vector
-:vxor.vv  vd, vs2, vs1, vm     is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
+:vxor.vv  vd, vs2, vs1^ vm     is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57  unimpl
 
 # vxor.vx        31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
 # vxor.vx vd, vs2, rs1, vm    # vector-scalar
-:vxor.vx  vd, vs2, rs1, vm     is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
+:vxor.vx  vd, vs2, rs1^ vm     is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57  unimpl
 
 # vzext.vf2      31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57
 # vzext.vf2 vd, vs2, vm  # Zero-extend SEW/2 source to SEW destination
-:vzext.vf2  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vzext.vf2  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vzext.vf4      31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57
 # vzext.vf4 vd, vs2, vm  # Zero-extend SEW/4 source to SEW destination
-:vzext.vf4  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vzext.vf4  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57  unimpl
 
 # vzext.vf8      31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57
 # vzext.vf8 vd, vs2, vm  # Zero-extend SEW/8 source to SEW destination
-:vzext.vf8  vd, vs2, vm   is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57  unimpl
+:vzext.vf8  vd, vs2^ vm   is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57  unimpl
 
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
index 749ac3e8e4..2cd1ab08e4 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
@@ -1,3 +1,587 @@
+attach variables [ r0711 r1519 r2024 r2731 ]
+       		 [ zero ra sp gp tp t0 t1 t2 s0 s1 a0  a1  a2 a3 a4 a5
+		   a6   a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
+
+attach variables [ cd0711NoSp ]
+       		 [ zero ra _ gp tp t0 t1 t2 s0 s1 a0  a1  a2 a3 a4 a5
+		   a6   a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];	   
+		   
+
+attach variables [ cr0206 cr0711 cd0711 ]
+       		 [ zero ra sp gp tp t0 t1 t2 s0 s1 a0  a1  a2 a3 a4 a5
+		   a6   a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ];
+
+attach variables [ cr0204s cr0709s cd0709s ]
+       		 [ s0 s1 a0 a1 a2 a3 a4 a5 ];
+
+
+attach variables [ fr0711 fr1519 fr2024 fr2731 ]
+       		 [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0  fa1  fa2 fa3 fa4  fa5
+		   fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
+
+attach variables [ cfr0206 cfr0711 ]
+       		 [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0  fa1  fa2 fa3 fa4  fa5
+		   fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
+
+attach variables [ cfr0204s cfr0709s ]
+       		 [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ];
+
+
+attach variables [ v0711 v1519 v2024 ]
+       		 [ v0  v1  v2  v3  v4  v5  v6  v7  v8  v9  v10 v11 v12 v13 v14 v15
+		   v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];
+
+#attach variables [ csr_0 ]
+#                 [ ustatus fflags frm fcsr uie utvec csr006 csr007
+#                   vstart vxsat  vxrm   csr00b csr00c csr00d csr00e vcsr
+#                   csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017
+#                   csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f
+#                   csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027
+#                   csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f
+#                   csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037
+#                   csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f
+#                   uscratch uepc ucause utval uip csr045 csr046 csr047
+#                   csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f
+#                   csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057
+#                   csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f
+#                   csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067
+#                   csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f
+#                   csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077
+#                   csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f
+#                   csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087
+#                   csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f
+#                   csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097
+#                   csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f
+#                   csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7
+#                   csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af
+#                   csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7
+#                   csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf
+#                   csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7
+#                   csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf
+#                   csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7
+#                   csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df
+#                   csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7
+#                   csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef
+#                   csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7
+#                   csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ];
+#attach variables [ csr_1 ]
+#                 [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107
+#                   csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f
+#                   csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117
+#                   csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f
+#                   csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
+#                   csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f
+#                   csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137
+#                   csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f
+#                   sscratch sepc scause stval sip csr145 csr146 csr147
+#                   csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f
+#                   csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157
+#                   csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f
+#                   csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
+#                   csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f
+#                   csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177
+#                   csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f
+#                   satp csr181 csr182 csr183 csr184 csr185 csr186 csr187
+#                   csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f
+#                   csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197
+#                   csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f
+#                   csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7
+#                   csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af
+#                   csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7
+#                   csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf
+#                   csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7
+#                   csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf
+#                   csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7
+#                   csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df
+#                   csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7
+#                   csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef
+#                   csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7
+#                   csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ];
+#attach variables [ csr_2 ]
+#                 [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207
+#                   csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f
+#                   csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217
+#                   csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f
+#                   csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227
+#                   csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f
+#                   csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237
+#                   csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f
+#                   vsscratch vsepc vscause vstval vsip csr245 csr246 csr247
+#                   csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f
+#                   csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257
+#                   csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f
+#                   csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267
+#                   csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f
+#                   csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277
+#                   csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f
+#                   vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287
+#                   csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f
+#                   csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297
+#                   csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f
+#                   csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7
+#                   csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af
+#                   csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7
+#                   csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf
+#                   csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7
+#                   csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf
+#                   csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7
+#                   csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df
+#                   csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7
+#                   csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef
+#                   csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7
+#                   csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ];
+#attach variables [ csr_3 ]
+#                 [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307
+#                   csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f
+#                   mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317
+#                   csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f
+#                   mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7
+#                   mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
+#                   mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23
+#                   mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
+#                   mscratch mepc mcause mtval mip csr345 csr346 csr347
+#                   csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f
+#                   csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357
+#                   csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f
+#                   csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367
+#                   csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f
+#                   csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377
+#                   csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f
+#                   mbase mbound mibase mibound mdbase mdbound csr386 csr387
+#                   csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f
+#                   csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397
+#                   csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f
+#                   pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7
+#                   pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15
+#                   pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7
+#                   pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
+#                   pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23
+#                   pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31
+#                   pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39
+#                   pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47
+#                   pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55
+#                   pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63
+#                   csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7
+#                   csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ];
+#attach variables [ csr_4 ]
+#                 [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407
+#                   csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f
+#                   csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417
+#                   csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f
+#                   csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427
+#                   csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f
+#                   csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437
+#                   csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f
+#                   csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447
+#                   csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f
+#                   csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457
+#                   csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f
+#                   csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467
+#                   csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f
+#                   csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477
+#                   csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f
+#                   csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487
+#                   csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f
+#                   csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497
+#                   csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f
+#                   csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7
+#                   csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af
+#                   csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7
+#                   csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf
+#                   csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7
+#                   csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf
+#                   csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7
+#                   csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df
+#                   csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7
+#                   csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef
+#                   csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7
+#                   csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ];
+#attach variables [ csr_50 ]
+#                 [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507
+#                   csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f
+#                   csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517
+#                   csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f
+#                   csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527
+#                   csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f
+#                   csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537
+#                   csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f
+#                   csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547
+#                   csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f
+#                   csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557
+#                   csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f
+#                   csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567
+#                   csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f
+#                   csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577
+#                   csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ];
+#attach variables [ csr_58 ]
+#                 [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587
+#                    csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f
+#                    csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597
+#                    csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f
+#                    csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7
+#                    scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af
+#                    csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7
+#                    csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ];
+#attach variables [ csr_5C ]
+#                 [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7
+#                   csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf
+#                   csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7
+#                   csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df
+#                   csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7
+#                   csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef
+#                   csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7
+#                   csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ];
+#attach variables [ csr_60 ]
+#                 [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie
+#                   csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f
+#                   csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617
+#                   csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f
+#                   csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627
+#                   csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f
+#                   csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637
+#                   csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f
+#                   csr640 csr641 csr642 htval  hip    hvip   csr646 csr647
+#                   csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f
+#                   csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657
+#                   csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f
+#                   csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667
+#                   csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f
+#                   csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677
+#                   csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ];
+#attach variables [ csr_68 ]
+#                 [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687
+#                   csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f
+#                   csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697
+#                   csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f
+#                   csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7
+#                   hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af
+#                   csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7
+#                   csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ];
+#attach variables [ csr_6C ]
+#                 [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7
+#                   csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf
+#                   csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7
+#                   csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df
+#                   csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7
+#                   csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef
+#                   csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7
+#                   csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ];
+#attach variables [ csr_70 ]
+#                 [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707
+#                   csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f
+#                   csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717
+#                   csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f
+#                   csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727
+#                   csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f
+#                   csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737
+#                   csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f
+#                   csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747
+#                   csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f
+#                   csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757
+#                   csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f
+#                   csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767
+#                   csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f
+#                   csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777
+#                   csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ];
+#attach variables [ csr_78 ]
+#                 [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787
+#                   csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f
+#                   csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797
+#                   csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ];
+#attach variables [ csr_7A ]
+#                 [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7
+#                   mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ];
+#attach variables [ csr_7B ]
+#                 [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7
+#                   csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ];
+#attach variables [ csr_7C ]
+#                 [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7
+#                   csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf
+#                   csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7
+#                   csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df
+#                   csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7
+#                   csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef
+#                   csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7
+#                   csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ];
+#attach variables [ csr_8 ]
+#                 [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807
+#                   csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f
+#                   csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817
+#                   csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f
+#                   csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827
+#                   csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f
+#                   csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837
+#                   csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f
+#                   csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847
+#                   csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f
+#                   csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857
+#                   csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f
+#                   csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867
+#                   csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f
+#                   csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877
+#                   csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f
+#                   csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887
+#                   csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f
+#                   csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897
+#                   csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f
+#                   csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7
+#                   csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af
+#                   csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7
+#                   csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf
+#                   csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7
+#                   csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf
+#                   csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7
+#                   csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df
+#                   csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7
+#                   csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef
+#                   csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7
+#                   csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ];
+#attach variables [ csr_90 ]
+#                 [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907
+#                   csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f
+#                   csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917
+#                   csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f
+#                   csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927
+#                   csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f
+#                   csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937
+#                   csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f
+#                   csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947
+#                   csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f
+#                   csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957
+#                   csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f
+#                   csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967
+#                   csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f
+#                   csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977
+#                   csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ];
+#attach variables [ csr_98 ]
+#                 [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987
+#                   csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f
+#                   csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997
+#                   csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f
+#                   csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7
+#                   csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af
+#                   csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7
+#                   csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ];
+#attach variables [ csr_9C ]
+#                 [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7
+#                   csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf
+#                   csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7
+#                   csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df
+#                   csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7
+#                   csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef
+#                   csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7
+#                   csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ];
+#attach variables [ csr_A0 ]
+#                 [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07
+#                   csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f
+#                   csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17
+#                   csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f
+#                   csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27
+#                   csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f
+#                   csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37
+#                   csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f
+#                   csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47
+#                   csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f
+#                   csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57
+#                   csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f
+#                   csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67
+#                   csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f
+#                   csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77
+#                   csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ];
+#attach variables [ csr_A8 ]
+#                 [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87
+#                   csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f
+#                   csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97
+#                   csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f
+#                   csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7
+#                   csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf
+#                   csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7
+#                   csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ];
+#attach variables [ csr_AC ]
+#                 [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7
+#                   csrac8 csrac9 csraca csracb csracc csracd csrace csracf
+#                   csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7
+#                   csrad8 csrad9 csrada csradb csradc csradd csrade csradf
+#                   csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7
+#                   csrae8 csrae9 csraea csraeb csraec csraed csraee csraef
+#                   csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7
+#                   csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ];
+#attach variables [ csr_B0 ]
+#                 [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7
+#                   mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
+#                   mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23
+#                   mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
+#                   csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27
+#		   csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f
+#		   csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37
+#		   csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f
+#                   csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47
+#                   csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f
+#                   csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57
+#                   csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f
+#                   csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67
+#                   csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f
+#                   csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77
+#                   csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ];
+#attach variables [ csr_B8 ]
+#                 [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h
+#                   mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h
+#                   mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h
+#                   mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h
+#                   csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7
+#                   csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf
+#                   csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7
+#                   csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ];
+#attach variables [ csr_BC ]
+#                 [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7
+#                   csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf
+#                   csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7
+#                   csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf
+#                   csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7
+#                   csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef
+#                   csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7
+#                   csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ];
+#attach variables [ csr_C0 ]
+#                 [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7
+#                   hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
+#                   hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23
+#                   hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
+#                   vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27
+#                   csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f
+#                   csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37
+#                   csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f
+#                   csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47
+#                   csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f
+#                   csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57
+#                   csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f
+#                   csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67
+#                   csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f
+#                   csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77
+#                   csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ];
+#attach variables [ csr_C8 ]
+#                 [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h
+#                   hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
+#                   hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h
+#                   hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
+#                   csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7
+#                   csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf
+#                   csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7
+#                   csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ];
+#attach variables [ csr_CC ]
+#                 [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7
+#                   csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf
+#                   csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7
+#                   csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf
+#                   csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7
+#                   csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef
+#                   csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7
+#                   csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ];
+#attach variables [ csr_D0 ]
+#                 [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07
+#                   csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f
+#                   csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17
+#                   csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f
+#                   csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27
+#                   csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f
+#                   csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37
+#                   csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f
+#                   csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47
+#                   csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f
+#                   csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57
+#                   csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f
+#                   csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67
+#                   csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f
+#                   csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77
+#                   csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ];
+#attach variables [ csr_D8 ]
+#                 [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87
+#                   csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f
+#                   csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97
+#                   csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f
+#                   csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7
+#                   csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf
+#                   csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7
+#                   csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ];
+#attach variables [ csr_DC ]
+#                 [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7
+#                   csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf
+#                   csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7
+#                   csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf
+#                   csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7
+#                   csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef
+#                   csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7
+#                   csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ];
+#attach variables [ csr_E0 ]
+#                 [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07
+#                   csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f
+#                   csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17
+#                   csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f
+#                   csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27
+#                   csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f
+#                   csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37
+#                   csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f
+#                   csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47
+#                   csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f
+#                   csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57
+#                   csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f
+#                   csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67
+#                   csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f
+#                   csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77
+#                   csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ];
+#attach variables [ csr_E8 ]
+#                 [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87
+#                   csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f
+#                   csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97
+#                   csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f
+#                   csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7
+#                   csrea8 csrea9 csreaa csreab csreac csread csreae csreaf
+#                   csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7
+#                   csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ];
+#attach variables [ csr_EC ]
+#                 [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7
+#                   csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf
+#                   csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7
+#                   csred8 csred9 csreda csredb csredc csredd csrede csredf
+#                   csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7
+#                   csree8 csree9 csreea csreeb csreec csreed csreee csreef
+#                   csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7
+#                   csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ];
+#attach variables [ csr_F0 ]
+#                 [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07
+#                   csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f
+#                   csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17
+#                   csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f
+#                   csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27
+#                   csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f
+#                   csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37
+#                   csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f
+#                   csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47
+#                   csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f
+#                   csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57
+#                   csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f
+#                   csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67
+#                   csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f
+#                   csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77
+#                   csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ];
+#attach variables [ csr_F8 ]
+#                 [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87
+#                   csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f
+#                   csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97
+#                   csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f
+#                   csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7
+#                   csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf
+#                   csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7
+#                   csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ];
+#attach variables [ csr_FC ]
+#                 [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7
+#                   csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf
+#                   csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7
+#                   csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf
+#                   csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7
+#                   csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef
+#                   csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7
+#                   csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ];
+
 
 #TODO  these names are madeup. do real ones exist?
 #TODO  go through and use these instead of numbers
@@ -177,6 +761,9 @@ aqrl: ".aqrl" is op2526=3 { export 3:$(XLEN); }
 crs1: cr0711 is cr0711 { export cr0711; }
 crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); }
 
+crdNoSp: cd0711NoSp is cd0711NoSp { export cd0711NoSp; }
+crdNoSp: zero is zero & cop0711=0 { export 0:$(XLEN); }
+
 crd: cd0711 is cd0711 { export cd0711; }
 crd: zero is zero & cop0711=0 { export 0:$(XLEN); }
 
@@ -254,117 +841,120 @@ csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ]
 # csr[11:10] - read/write (00, 01, 10) or read-only (11)
 # csr[9:8] - lowest privilege that can access the CSR
 
-# 0x000-0x0ff
-with csr: op3031=0 & op2829=0 {
-	: csr_0 is csr_0 { export csr_0; } # user, standard read/write
-}
+## 0x000-0x0ff
+#with csr: op3031=0 & op2829=0 {
+#	: csr_0 is csr_0 { export csr_0; } # user, standard read/write
+#}
+#
+## 0x100-0x1ff
+#with csr: op3031=0 & op2829=1 {
+#	: csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write
+#}
+#
+## 0x200-0x2ff
+#with csr: op3031=0 & op2829=2 {
+#	: csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write
+#}
+#
+## 0x300-0x3ff
+#with csr: op3031=0 & op2829=3 {
+#	: csr_3 is csr_3 { export csr_3; } # machine, standard read/write
+#}
+#
+## 0x400-0x4ff
+#with csr: op3031=1 & op2829=0 {
+#	: csr_4 is csr_4 { export csr_4; } # user, standard read/write
+#}
+#
+## 0x500-0x5ff
+#with csr: op3031=1 & op2829=1 {
+#	: csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write
+#	: csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write
+#	: csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write
+#}
+#
+## 0x600-0x6ff
+#with csr: op3031=1 & op2829=2 {
+#	: csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write
+#	: csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write
+#	: csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write
+#}
+#
+## 0x700-0x7ff
+#with csr: op3031=1 & op2829=3 {
+#	: csr_70 is csr_70 & op2727=0   { export csr_70; } # machine, standard read/write
+#	: csr_78 is csr_78 & op2527=4   { export csr_78; } # machine, standard read/write
+#	: csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug
+#	: csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only
+#	: csr_7C is csr_7C & op2627=3   { export csr_7C; } # machine, custom read/write
+#}
+#
+## 0x800-0x8ff
+#with csr: op3031=2 & op2829=0 {
+#	: csr_8 is csr_8 { export csr_8; } # user, custom read/write
+#}
+#
+## 0x900-0x9ff
+#with csr: op3031=2 & op2829=1 {
+#	: csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write
+#	: csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write
+#	: csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write
+#}
+#
+## 0xa00-0xaff
+#with csr: op3031=2 & op2829=2 {
+#	: csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write
+#	: csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write
+#	: csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write
+#}
+#
+## 0xb00-0xbff
+#with csr: op3031=2 & op2829=3 {
+#	: csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write
+#	: csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write
+#	: csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write
+#}
+#
+## 0xc00-0xcff
+#with csr: op3031=3 & op2829=0 {
+#	: csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only
+#	: csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only
+#	: csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only
+#}
+#
+## 0xd00-0xdff
+#with csr: op3031=3 & op2829=1 {
+#	: csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only
+#	: csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only
+#	: csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only
+#}
+#
+## 0xe00-0xeff
+#with csr: op3031=3 & op2829=2 {
+#	: csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only
+#	: csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only
+#	: csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only
+#}
+#
+## 0xf00-0xfff
+#with csr: op3031=3 & op2829=3 {
+#	: csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only
+#	: csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only
+#	: csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only
+#}
+#
 
-# 0x100-0x1ff
-with csr: op3031=0 & op2829=1 {
-	: csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write
-}
+csr: csr_reg is op2031 [ csr_reg = $(CSR_REG_START) + op2031; ] { export *[csreg]:$(XLEN) csr_reg; }
 
-# 0x200-0x2ff
-with csr: op3031=0 & op2829=2 {
-	: csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write
-}
-
-# 0x300-0x3ff
-with csr: op3031=0 & op2829=3 {
-	: csr_3 is csr_3 { export csr_3; } # machine, standard read/write
-}
-
-# 0x400-0x4ff
-with csr: op3031=1 & op2829=0 {
-	: csr_4 is csr_4 { export csr_4; } # user, standard read/write
-}
-
-# 0x500-0x5ff
-with csr: op3031=1 & op2829=1 {
-	: csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write
-	: csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write
-	: csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write
-}
-
-# 0x600-0x6ff
-with csr: op3031=1 & op2829=2 {
-	: csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write
-	: csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write
-	: csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write
-}
-
-# 0x700-0x7ff
-with csr: op3031=1 & op2829=3 {
-	: csr_70 is csr_70 & op2727=0   { export csr_70; } # machine, standard read/write
-	: csr_78 is csr_78 & op2527=4   { export csr_78; } # machine, standard read/write
-	: csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug
-	: csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only
-	: csr_7C is csr_7C & op2627=3   { export csr_7C; } # machine, custom read/write
-}
-
-# 0x800-0x8ff
-with csr: op3031=2 & op2829=0 {
-	: csr_8 is csr_8 { export csr_8; } # user, custom read/write
-}
-
-# 0x900-0x9ff
-with csr: op3031=2 & op2829=1 {
-	: csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write
-	: csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write
-	: csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write
-}
-
-# 0xa00-0xaff
-with csr: op3031=2 & op2829=2 {
-	: csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write
-	: csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write
-	: csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write
-}
-
-# 0xb00-0xbff
-with csr: op3031=2 & op2829=3 {
-	: csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write
-	: csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write
-	: csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write
-}
-
-# 0xc00-0xcff
-with csr: op3031=3 & op2829=0 {
-	: csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only
-	: csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only
-	: csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only
-}
-
-# 0xd00-0xdff
-with csr: op3031=3 & op2829=1 {
-	: csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only
-	: csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only
-	: csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only
-}
-
-# 0xe00-0xeff
-with csr: op3031=3 & op2829=2 {
-	: csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only
-	: csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only
-	: csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only
-}
-
-# 0xf00-0xfff
-with csr: op3031=3 & op2829=3 {
-	: csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only
-	: csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only
-	: csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only
-}
-
-
-
-vm: op2525 is op2525 { local tmp:1 = op2525; export tmp; }
 
 vs1: v1519 is v1519 { export v1519; }
 vs2: v2024 is v2024 { export v2024; }
 vs3: v0711 is v0711 { export v0711; }
 vd:  v0711 is v0711 { export v0711; }
 
+vm: ,v0^".t" is op2525=0 & v0 & vd { vd = vd & v0; }
+vm: "" is op2525=1 { }
+
 simm5: sop1519 is sop1519 { local tmp:$(XLEN) = sop1519; export tmp; }
 # zimm: op1519 is op1519 { local tmp:$(XLEN) = op1519; export tmp; }
 
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec
index fcab73299f..927b8ea4b3 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec
@@ -22,6 +22,7 @@
   </data_organization>
   <global>
     <range space="ram"/>
+    <range space="csreg"/>
     <register name="gp"/>
     <register name="tp"/>
   </global>
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32.cspec b/Ghidra/Processors/RISCV/data/languages/riscv32.cspec
index 7686bf9b9a..5f820af9fb 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv32.cspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv32.cspec
@@ -20,6 +20,7 @@
   </data_organization>
   <global>
     <range space="ram"/>
+    <range space="csreg"/>
     <register name="gp"/>
     <register name="tp"/>
   </global>
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec
index c01a51e02f..fd17e478a2 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec
@@ -22,6 +22,7 @@
   </data_organization>
   <global>
     <range space="ram"/>
+    <range space="csreg"/>
     <register name="gp"/>
     <register name="tp"/>
   </global>
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64.cspec b/Ghidra/Processors/RISCV/data/languages/riscv64.cspec
index ec263444bb..90970af997 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv64.cspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv64.cspec
@@ -18,11 +18,14 @@
 		<entry size="8" alignment="8" />
 	</size_alignment_map>
   </data_organization>
+  
   <global>
     <range space="ram"/>
+    <range space="csreg"/>
     <register name="gp"/>
     <register name="tp"/>
   </global>
+  
   <returnaddress>
     <register name="ra"/>
   </returnaddress>