c18a58b2af
Merge remote-tracking branch 'origin/GP-6501_ghidorahrex_mips32_save_restore--SQUASHED' into patch
2026-02-27 20:28:01 -05:00
cbc000b2a0
GP-6501: Fixed up mfc0/mtc0 semantics. Added MIPS32 save/restore instructions
2026-02-27 23:01:19 +00:00
456fde450b
Merge remote-tracking branch 'origin/GP-6489_ghidorahrex_mips16_sdbbp16_fix' into patch
2026-02-25 12:48:05 -05:00
2ad8259a29
GP-6489: Fixed opcode for MIPS sdbbp16 instruction
2026-02-25 13:24:42 +00:00
0079da9835
Merge remote-tracking branch 'origin/GP-6080_ghidorahrex_Xtensa_bigendian_fix' into patch
2026-02-25 04:48:00 -05:00
96564d1be5
Merge remote-tracking branch
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'origin/GP-6448_ghidorahrex_AARCH64_CSSC_instructions--SQUASHED' into
patch (Closes #8973 , Closes #8979 )
2026-02-24 12:41:59 -05:00
ea52a687b2
GP-6448: Added AARCH64 CSSC instructions
2026-02-24 10:49:41 -05:00
823993e9e1
Merge remote-tracking branch
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'origin/GP-6473_ghidorahrex_PR-6467_Sleigh-InSPECtor_aa64_ldar_ld_size'
into patch (Closes #6467 , Closes #8014 )
2026-02-23 10:20:11 -05:00
3fbe33860b
AA64: fix ldar load size for 32bit variant
2026-02-23 14:53:22 +00:00
bbe8d7ca93
AA64: fix ldpsw increment size to match load
2026-02-20 18:17:38 +00:00
a71300ffdf
Merge remote-tracking branch
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'origin/GP-6181_ghidorahrex_PR-8716_Jomosoto_cr16c-tbit' into patch
(Closes #8716 )
2026-02-12 12:53:37 -05:00
c0fe936573
Merge remote-tracking branch
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'origin/GP-6004_ghidorahrex_PR-8501_robbederks_pic18-fix-incdec' into
patch (Closes #3342 , Closes #8501 )
2026-02-11 05:52:27 -05:00
aa8e098ad5
Merge remote-tracking branch
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'origin/GP-6268_ghidorahrex_PR-8821_0dinD_altivec-vadduws' into patch
(Closes #8821 )
2026-02-11 05:45:54 -05:00
53beea47b3
Merge remote-tracking branch
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'origin/GP-6182_ghidorahrex_PR-8721_niooss-ledger_ebpf-fix-disassembly-atomic-instructions'
into patch (Closes #8721 )
2026-02-11 05:43:51 -05:00
2b20282f44
Merge remote-tracking branch 'origin/GP-6419_ghidorahrex_MIPS16_pcodetest_fix' into patch
2026-02-09 11:43:03 -05:00
adbd7fcfed
Merge remote-tracking branch
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'origin/GP-5905_ghidorahrex_80251_fix_SPX_instructions' into patch
(Closes #8395 )
2026-02-09 11:21:37 -05:00
1660b9ca47
GP-6419: Fixed MIPS16 pcodetest failures
2026-02-09 15:33:05 +00:00
08c8a507b6
Merge remote-tracking branch
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'origin/GP-4501_ghidorahrex_PR-6398_Sleigh-InSPECtor_aa64_sha1h_rotate'
into patch (Closes #6398 )
2026-01-30 13:24:20 -05:00
c9be1860c1
AArch32: fixed ldrexd
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* fixed addr src register aliased as first dest register of a double word load causing second word load at the value of first load
2026-01-27 17:28:22 +00:00
c0bc9a882b
PowerPC VLE: Fix se_blrl flow
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Opcode se_blrl is branch link register and link. Treating it as a return break flow and is wrong. Non VLE is already correct.
2026-01-26 19:28:15 +00:00
b5fb4d36ed
AA64: Add ls_data8 to ldapr
2026-01-22 13:31:11 +00:00
fe35e34add
GP-6329 Corrected PowerPC-32 ELF Relocation processing for
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R_PPC_ADDR16_LO and R_PPC_ADDR16_HA
2026-01-13 17:16:14 -05:00
6208df2d50
GP-1 Corrected RISCV import opinion file
2026-01-13 10:44:59 -05:00
e94681701a
CR16: fix CR16C TBIT instruction
2025-12-29 20:10:09 +00:00
af8a370421
Fix eBPF compare-and-exchange instruction
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Linux kernel's documentation tells in
https://www.kernel.org/doc/html/v6.0/bpf/instruction-set.html#atomic-operations
> The BPF_CMPXCHG operation atomically compares the value addressed by
> dst_reg + off with R0. If they match, the value addressed by
> dst_reg + off is replaced with src_reg. In either case, the value that
> was at dst_reg + off before the operation is zero-extended and loaded
> back to R0.
If the values don't match, *(dst_reg + off) is not supposed to be
modified.
Moreover, register R0 is always modified and the 32-bit instruction
truncates its value (with a zero-extension). This is also clear in the
implementation of BPF_CMPXCHG in
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/bpf/core.c?h=v6.18#n2186
case BPF_CMPXCHG:
if (BPF_SIZE(insn->code) == BPF_W)
BPF_R0 = (u32) atomic_cmpxchg(
(atomic_t *)(unsigned long) (DST + insn->off),
(u32) BPF_R0, (u32) SRC);
else if (BPF_SIZE(insn->code) == BPF_DW)
BPF_R0 = (u64) atomic64_cmpxchg(
(atomic64_t *)(unsigned long) (DST + insn->off),
(u64) BPF_R0, (u64) SRC);
Fix the semantic of the compare-and-exchange instruction accordingly.
2025-12-29 19:49:13 +00:00
ff6eb2213b
Fix disassembly of eBPF atomic instructions
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eBPF ISA v3 introduced atomic instructions:
https://www.kernel.org/doc/html/v6.0/bpf/instruction-set.html#atomic-operations
These instructions are encoded using BPF_ATOMIC | BPF_W | BPF_STX
and BPF_ATOMIC | BPF_DW | BPF_STX for 32-bit and 64-bit operations,
with:
BPF_ATOMIC = 0xc0
BPF_DW = 0x18
BPF_W = 0
BPF_STX = 0x03
While Ghidra's semantic section is constructed correctly (atomic add
uses an addition ; atomic or uses or ; ...), the disassembly always
displays STXXADDW and STXXADDDW. These mnemonics come from the
deprecated name BPF_XADD = BPF_ATOMIC | BPF_ADD = 0xc0.
Replace the confusing mnemonics with the ones used by binutils and
documented in
https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/doc/c-bpf.texi;h=003cb92a457985038a9abc1ffbf347f636eb0586;hb=2bc7af1ff7732451b6a7b09462a815c3284f9613#l745
2025-12-29 19:49:12 +00:00
c1f97cde08
Fix missing Altivec vadduws instruction
2025-12-23 13:21:07 +00:00
c981c0b5dd
GP-6004: Refactored out duplicated constructors
2025-12-16 20:07:56 +00:00
ba9c648374
GP-6229 Updated EmulateInstructionStateModifier.executeCallOther to drop first input for consistency with all other code that invokes OpBehaviorOther.evaluate method and Corrected OpBehaviorOther regression errors with various implementations
2025-12-15 15:20:37 -05:00
78859d55fd
GP-5905: Fixed issue with 80251 instructions referencing SPX register
2025-12-12 14:52:29 +00:00
b4ecdc6d9e
Merge remote-tracking branch
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'origin/GP-5334_ghidorahrex_m68k_addrmode_operand_fix' into patch
(Closes #4358 )
2025-12-09 14:04:27 -05:00
27b06c83a6
GP-5334: Corrected operand count for m68k addressing modes
2025-12-09 19:01:17 +00:00
6504c296b2
Merge remote-tracking branch
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'origin/GP-6109_ghidorahrex_powerpc_vle_assembly_fix' into patch
(Closes #8624 )
2025-12-09 12:32:36 -05:00
d0f88bf902
GP-6007 Remove Decompiler dependency
2025-12-04 12:28:50 -05:00
923ceb52d4
GP-6007 use -l sleigh compile option with NDS32
2025-12-04 11:25:54 -05:00
ddf4ad1182
GP-6007 minor fixes for Andestar v5
2025-12-03 22:06:38 +00:00
2efa886f5c
GP-6007 minor fixes for mfusr, mtusr and csreg space as global in cspec
2025-12-03 21:36:18 +00:00
df6e4049d4
GP-6007: Added additional floating point config instructions
2025-12-02 20:34:41 +00:00
9bdd19cc08
GP-6007: Added CSR space and CSRs
2025-12-02 15:49:55 +00:00
ed4ae8bfa1
GP-6007: Added stubs for nds32 FPU instructions
2025-11-26 20:19:40 +00:00
71cd33572c
GP-6007: Updated NDS32 analyzer and elf relocation handler and test
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fixups
2025-11-26 15:59:55 +00:00
fa7c3b1fec
[NDS32] Add support for the NDS32 Processor
2025-11-26 15:59:54 +00:00
9499199f83
Merge remote-tracking branch 'origin/GP-6120_emteere_PPC64ThunkPatterns' into Ghidra_12.0
2025-11-26 05:01:09 -05:00
e1f6642c77
Merge remote-tracking branch
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'origin/GP-6121_ghidorahrex_PR-8625_dt-12345_aarch64_fmadd' into
Ghidra_12.0 (Closes #8625 , Closes #8454 )
2025-11-24 14:01:25 -05:00
00978223d3
Merge remote-tracking branch
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'origin/GP-4650_ghidorahrex_PR-6544_Sleigh-InSPECtor_aarch32_vmvn' into
Ghidra_12.0 (Closes #6544 )
2025-11-24 13:58:19 -05:00
88ff4b2008
GP-6120_emteere_FixThunkDetectionMarkupPPC64
2025-11-24 18:25:40 +00:00
22a5a22d82
PowerPC: fix condition check in bd*f* opcodes
2025-11-20 12:39:15 -05:00
0982753437
AArch32: fixed vmvn
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* fixed incorrect shift offset (bytes given in place of bits) and double word order
2025-11-20 15:19:00 +00:00
c4c7f11d1c
fix AArch64 fmadd operand ordering for 32-bit case
2025-11-14 17:07:20 +00:00
5857e63741
GP-6118 Fix for specialized ARM cpy pc,lr
2025-11-13 20:31:53 +00:00
ghidra1