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Language fixes for inconsistent 0 size exports

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This commit is contained in:
caheckman
2023-03-13 15:08:39 -04:00
parent 349b891165
commit 6c761536ba
3 changed files with 9 additions and 9 deletions
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10
Ghidra/Processors/Atmel/data/languages/avr32a.slaspec
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@@ -637,19 +637,19 @@ RBSelector: rb9[ri0"<U> << 2]" is rb9 & ri0; selectorxy4_2=0x2 { ptr:4 = rb9 + (
RBSelector: rb9[ri0"<T> << 2]" is rb9 & ri0; selectorxy4_2=0x3 { ptr:4 = rb9 + (((ri0 >> 24) & 0xff) << 0x02); export ptr; }
RS0A: rs0 is rs0 { export rs0; }
RS0A: rs0 is rs0 & rs0=0xf { export inst_start; }
RS0A: rs0 is rs0 & rs0=0xf { export *[const]:4 inst_start; }
RS9A: rs9 is rs9 { export rs9; }
RS9A: rs9 is rs9 & rs9=0xf { export inst_start; }
RS9A: rs9 is rs9 & rs9=0xf { export *[const]:4 inst_start; }
RX9A: rx9 is rx9 { export rx9; }
RX9A: rx9 is rx9 & rx9=0xf { export inst_start; }
RX9A: rx9 is rx9 & rx9=0xf { export *[const]:4 inst_start; }
RY0A: ry0 is ry0 { export ry0; }
RY0A: ry0 is ry0 & ry0=0xf { export inst_start; }
RY0A: ry0 is ry0 & ry0=0xf { export *[const]:4 inst_start; }
RD0A: rd0 is rd0 { export rd0; }
RD0A: rd0 is rd0 & rd0=0xf { export inst_start; }
RD0A: rd0 is rd0 & rd0=0xf { export *[const]:4 inst_start; }
macro ZSTATUS(RES) {
Z = RES == 0;

2
Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations.sinc
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@@ -18,7 +18,7 @@ rdPlus1: is erd0=0x6 {export R7;}
rdPlus1: is erd0=0x8 {export R9;}
rdPlus1: is erd0=0xa {export R11;}
rdPlus1: is erd0=0xc {export SP;}
rdPlus1: is erd0=0xe {export inst_start;}#PC register
rdPlus1: is erd0=0xe {export *[const]:4 inst_start;}#PC register
#---------------------------------------------------------------------
# ADDHH.W - Add Halfwords into Word

6
Ghidra/Processors/MC6800/data/languages/6x09.sinc
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@@ -197,11 +197,11 @@ EA: ",--"^W is idxReg=0b11 & noOffset5=1 & idxMode=0b01111 & W # ,--W
EA: addr,"PCR" is noOffset5=1 & idxMode=0b01100; simm8 [ addr = inst_next + simm8; ]
{
export addr;
export *[const]:2 addr;
}
EA: addr,"PCR" is noOffset5=1 & idxMode=0b01101; simm16 [ addr = inst_next + simm16; ]
{
export addr;
export *[const]:2 addr;
}
EA: "[,"idxReg"]" is idxReg & noOffset5=1 & idxMode=0b10100
{
@@ -394,7 +394,7 @@ OP2J: EA is (op47=6 | op47=0xA); EA
}
OP2J: imm16 is (op47=7 | op47=0xB ); imm16
{
export imm16;
export *[const]:2 imm16;
}
################################################################