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GP-3068 Adding in pure 32-bit PPC e500mc processor spec

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This commit is contained in:
emteere
2023-12-15 02:55:39 +00:00
parent fcb2f6a1fa
commit ec023b3ffe
6 changed files with 238 additions and 0 deletions
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4
Ghidra/Processors/PowerPC/certification.manifest
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@@ -28,6 +28,10 @@ data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_e500mc_be.cspec||GHIDRA||||END|
data/languages/ppc_32_e500mc_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_e500mc_le.cspec||GHIDRA||||END|
data/languages/ppc_32_e500mc_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_le.cspec||GHIDRA||||END|
data/languages/ppc_32_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_mpc8270.pspec||GHIDRA||||END|

30
Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
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@@ -206,6 +206,36 @@
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
endian="big"
size="32"
variant="PowerQUICC-III-e500mc"
version="1.5"
slafile="ppc_32_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
id="PowerPC:BE:32:e500mc">
<description>PowerQUICC-III e500mc 32-bit big-endian family</description>
<compiler name="default" spec="ppc_32_e500mc_be.cspec" id="default"/>
<external_name tool="gnu" name="powerpc:e500mc"/>
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
endian="little"
size="32"
variant="PowerQUICC-III-e500mc"
version="1.5"
slafile="ppc_32_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
id="PowerPC:LE:32:e500mc">
<description>PowerQUICC-III e500mc 32-bit little-endian family</description>
<compiler name="default" spec="ppc_32_e500mc_le.cspec" id="default"/>
<external_name tool="gnu" name="powerpc:e500mc"/>
<external_name tool="IDA-PRO" name="ppc"/>
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
</language>
<language processor="PowerPC"
endian="big"
size="32"

80
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec Normal file
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@@ -0,0 +1,80 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="r1" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input pointermax="4">
<pentry minsize="1" maxsize="4">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r7"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r8"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r10"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r3" piece2="r4"/>
</pentry>
</output>
<unaffected>
<register name="r14"/>
<register name="r15"/>
<register name="r16"/>
<register name="r17"/>
<register name="r18"/>
<register name="r19"/>
<register name="r20"/>
<register name="r21"/>
<register name="r22"/>
<register name="r23"/>
<register name="r24"/>
<register name="r25"/>
<register name="r26"/>
<register name="r27"/>
<register name="r28"/>
<register name="r29"/>
<register name="r30"/>
<register name="r31"/>
<register name="r1"/>
<register name="cr4"/>
</unaffected>
</prototype>
</default_proto>
<callfixup name="get_pc_thunk_lr">
<pcode>
<body><![CDATA[
LR = inst_dest + 4;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

23
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec Normal file
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@@ -0,0 +1,23 @@
# SLA specification file for IBM PowerPC e500 series core
# NOTE: This language variant includes some registers and instructions not supported
# by the actual processor (e.g., floating pointer registers and associated instructions).
# The actual processor only supports a subset of the registers and instructions implemented.
@define ENDIAN "big"
@define REGISTER_SIZE "4"
@define EATRUNC "ea"
# e500mc has 32 bit registers
#
@define CTR_OFFSET "32"
@define NoLegacyIntegerMultiplyAccumulate
@include "ppc_common.sinc"
@include "quicciii.sinc"
@include "evx.sinc"
@include "SPEF_SCR.sinc"

80
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec Normal file
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@@ -0,0 +1,80 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="r1" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input pointermax="4">
<pentry minsize="1" maxsize="4">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r7"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r8"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="r10"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r4" piece2="r3"/>
</pentry>
</output>
<unaffected>
<register name="r14"/>
<register name="r15"/>
<register name="r16"/>
<register name="r17"/>
<register name="r18"/>
<register name="r19"/>
<register name="r20"/>
<register name="r21"/>
<register name="r22"/>
<register name="r23"/>
<register name="r24"/>
<register name="r25"/>
<register name="r26"/>
<register name="r27"/>
<register name="r28"/>
<register name="r29"/>
<register name="r30"/>
<register name="r31"/>
<register name="r1"/>
<register name="cr4"/>
</unaffected>
</prototype>
</default_proto>
<callfixup name="get_pc_thunk_lr">
<pcode>
<body><![CDATA[
LR = inst_dest + 4;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

21
Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec Normal file
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@@ -0,0 +1,21 @@
# SLA specification file for IBM PowerPC e500 series core
#@define E500
@define ENDIAN "little"
@define REGISTER_SIZE "4"
@define EATRUNC "ea"
# e500mc has 32 bit registers
#
@define CTR_OFFSET "32"
@define NoLegacyIntegerMultiplyAccumulate
@include "ppc_common.sinc"
@include "quicciii.sinc"
@include "evx.sinc"
@include "SPEF_SCR.sinc"